Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-01-06
2000-03-14
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438631, 438624, 438645, 438697, 438699, 438734, H01L 214763
Patent
active
060372516
ABSTRACT:
A process for intermetal SOG/SOP dielectric planarization without having effect is described. First, a silicon-rich oxide (SRO) layer is formed on a substrate surface. Next, a metal layer and an antireflective coating (ARC) layer are sequentially deposited over the SRO layer. The metal layer and ARC layer are then etched to define metal patterns by the conventional lithography and etching techniques. Next, an Ozone-TEOS (O.sub.3 -TEOS) layer and a SOG layer are then formed over the entire substrate surface. Next, the O.sub.3 -TEOS layer and SOG layer are subjected to etching back treatment to obtain a planar substrate surface which only has a small portion of the O.sub.3 -TEOS layer covered on the substrate surface. The etching back treatment can be PEB, TEB or CMP techniques. Finally, a passivation layer is deposited over the remaining of O.sub.3 -TEOS layer.
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Huang Dinos
Kuang-Chao Chen
Tu Tuby
Wu Chin-Ta
Mosel Vitelic Inc.
Niebling John F.
Simkovic Viktor
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