Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-10-01
2004-07-13
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S015000, C710S052000, C710S053000, C710S054000, C710S055000, C710S056000, C710S072000
Reexamination Certificate
active
06763405
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the interfacing of a microprocessor with a device operating according to packet-based communication criteria.
The invention has been developed paying particular attention to its possible application to the interfacing of a microprocessor with a Link Layer 1394 device, namely a device operating according to the high-speed communication specifications defined in the IEEE 1394 standard.
DESCRIPTION OF THE PRIOR ART
When a microprocessor is to be connected to a device with high-speed data transmission characteristics (for example, a peripheral unit for real-time audio/video applications), it is current practice to resort to a packet-based communication mechanism.
The packets are transmitted in a synchronous way with a clock signal with the aim of maximizing transmission throughput to the peripheral, which operates according to a packet protocol.
There may, however, arise situations (for example, a memory-access stall) such as to render momentarily unavailable the packet to be transmitted. This results in a de-assertion of the corresponding validation signal, with a consequent transmission delay.
Prior documents, such as U.S. Pat. No. 5,842,027, tackle the problem of interfacing with USB devices. Other documents, such as U.S. Pat. No. 5,483,656, U.S. Pat. No. 5,752,046 and U.S. Pat. No. 6,061,746 tackle more in general the problem of “power management” in a context which, to a certain extent, is akin to that of the present invention. However, none of the above-cited documents deals in a specific way with the problem underlying the present invention.
OBJECT AND SUMMARY OF THE PRESENT INVENTION
The object of the present invention is, then, to achieve interfacing of a microprocessor with one or more high-speed peripherals operating according to a packet protocol in such a way as to maximize transmission throughput and speed in communication.
In accordance with the present invention, the above object is achieved thanks to a process having the characteristics specifically called for in the claims which follow.
The invention also relates to the corresponding system.
Basically, the solution according to the invention aims at maximizing throughput by minimizing (in actual fact, eliminating) possible gaps or discontinuities that may occur both in data transmission and in data reception within data packets and between sets of successive data packets
In the currently preferred embodiment, the solution according to the invention envisages the creation of an interface containing a dedicated memory, whilst the packets are transmitted on the basis of packet size. The dedicated memory “smooths” the delays in the communication between the main memory and the interfacing block proper (for example, a Link Layer Interface (LLI) operating in compliance with the IEEE 1394 standard).
Preferably, this memory has a software-programmable trigger which makes it possible to initiate a communication according to the level of filling of the memory, i.e., when a fraction of the memory or the entire memory is full/empty. In addition, when a multiple packet is being transferred, a signal is used for alerting the microprocessor of the fact that a transfer is nearly complete.
In a particularly preferred embodiment, the solution according to the invention envisages joint recourse to:
a minimization function for minimizing delays during packet transmission, the said function being implemented by using a dedicated internal memory (preferably organized as a FIFO memory), with recourse to a programmable (via software) signal indicating the state of the internal memory;
read-only “shadow” registers containing the current address to be transferred; in this way, the registers that are to be written for the subsequent transfer can be updated before the transfer in progress is through; and
an interrupt signal indicating that the transfer is nearly complete, this interrupt can be generated before the transfer is completed, and this enables the next transfer to be programmed before the current transfer is through.
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patent: 5745707 (1998-04-01), Takahashi
patent: 5859980 (1999-01-01), Kalkunte
patent: 6223266 (2001-04-01), Sartore
patent: 6324595 (2001-11-01), Tsai et al.
patent: 6434645 (2002-08-01), Parvin et al.
patent: WO 94/02900 (1994-02-01), None
European Search Report from priority European patent application No. 00830657, filed Oct. 6, 2000.
Miritello Rosario
Sardo Michele
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Farooq Mohammad O.
Gaffin Jeffrey
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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