Process for generating a variable frequency signal, for...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C327S158000

Reexamination Certificate

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07079616

ABSTRACT:
The use of a PLL including a phase detector responsive to the phase difference between an input signal and a feedback signal and which pilots an oscillator in function of this difference, is envisaged. The PLL also includes a feedback path that is responsive to the signal generated by the oscillator and which generates said feedback signal via at least one divider with a variable division ratio. The division ratio of said divider is modulated via a sigma-delta modulator, the input of which is fed with a triangular-wave modulating signal. The preferred application is that of a spread spectrum clock generator (SSCG) for digital electronic systems.

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T. Musch, et al., “A Highly Linear Frequency Ramp Genrator Based on A Fractional Divider Phase-Locked-Loop”, IEEE Transactions on Instrumentation and Measurement, IEEE Inc., New York, U.S., vol. 48, No. 2, Apr. 1999, pp. 634-637.

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