Process for forming twin well CMOS integrated circuits

Details Process for forming twin well CMOS integrated circuits Process for forming twin well CMOS integrated circuits

1992-08-12

1993-09-21

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257372, 257506, 257921, H01L 2702, H01L 2906, H01L 2910, H01L 2934

Patent

active

052471993

ABSTRACT:
A complementary insulated gate field effect transistor comprises a semiconductor body having an effectively planar surface, the semiconductor body containing complementary conductivity type wells in which complementary transistors are formed. A field insulator layer is selectively formed on the surface of the body, the field insulator layer being hardened against radiation. That portion of the planar surface of the body on which the field insulator layer is formed is not lower than respective surface portions on which first and second gate insulator layers of the complementary conductivity type transistors are formed. In addition to respective gates, and source and drain region pairs, the complementary transistors have insulative spacers which abut sidewalls of the first and second gates and the field insulator layer and extend over portions of the source and drain regions.

REFERENCES:
patent: 3754168 (1973-08-01), Cunningham et al.
patent: 3882530 (1975-05-01), Danchenko
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4318750 (1982-03-01), Rai-Choudhury et al.
patent: 4442591 (1984-04-01), Haken
patent: 4474624 (1984-10-01), Matthews
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4599789 (1986-07-01), Gasner
patent: 4633289 (1986-12-01), Yuan-Tai Chen
IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 541-547 "Direct Moat Isolation for VLSI" by Wang et al.

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