Process for forming TiSi.sub.2 layers of differing thicknesses i

Details Process for forming TiSi.sub.2 layers of differing thicknesses i Process for forming TiSi.sub.2 layers of differing thicknesses i

1984-11-30

1986-05-13

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29590, 29577C, H01L 21285

Patent

active

045877181

ABSTRACT:
Using a process in accordance with the teachings of this invention, an integrated circuit may be fabricated providing refractory metal silicide layers, such as TiSi.sub.2, of differing thicknesses to provide optimal reductions in the sheet resistances of the regions in which refractory metal silicide layers are formed. In one embodiment of the present invention a field effect transistor having a polycrystalline silicon gate is fabricated to provide a gate having optimally minimized sheet resistance and source and drain regions having TiSi.sub.2 layers of the appropriate thickness to avoid punch-through leakage problems.

REFERENCES:
patent: 3274670 (1966-09-01), Lepselter
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4510670 (1985-04-01), Schwabe et al.
IBM Technical Disclosure Bulletin vol. 13, No.3, Aug. 1970, p. 646, Kircher et al., "Fabricating a Gate Field-Effect Transistor".
IBM Technical Disclosure Bulletin vol. 23, No. 6, Nov. 1980, pp. 2563-2566 Rideout "Method of Fabricating MOSFET . . . ".

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