Process for forming silicon on insulator devices having elevated

Details Process for forming silicon on insulator devices having elevated Process for forming silicon on insulator devices having elevated

1997-08-20

1999-02-09

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

H01L 2184

Patent

active

058693599

ABSTRACT:
A dielectric layer is formed over an SOI layer and then masked and etched to define a trench. The sidewalls of the trench are thermally oxidized to form a layer of oxide thereon. A polysilicon gate is then formed within the trench. The layer of oxide laterally bounds the gate and thus serves a sidewall spacer for the gate. Dopants are implanted into portions of the SOI layer lying on opposite sides of the trench to form elevated source and drain regions. A layer of silicide such as, for instance, titanium silicide, may then be formed within surface portions of the elevated source and drain. The elevation of the source and drain allows silicon to be sufficiently sourced during formation of the silicide, thereby minimizing agglomeration within the silicide layer. The channel length of a semiconductor device fabricated using present embodiments is controlled by the thickness of the sidewall spacer.

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patent: 5434093 (1995-07-01), Chau et al.
patent: 5461243 (1995-10-01), Ek et al.
patent: 5545579 (1996-08-01), Liang et al.
Wolf et al., "Silicon Processing for the VLSI Era vol. 1:Prcess Technology" Lattice Press, Sunset Beach, CA USA. pp. 280-299, 1986 No month.
Wolf "Silicon Processing for the VLSI Era vol. 2:Process Integration" Lattice Press, Sunset Beach, CA USA. pp. 66-69, 1990 No month.

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