Electrical connectors – Contact comprising cutter – Resiliently biased
Reexamination Certificate
2001-08-21
2003-05-13
Whitehead, Jr., Carl (Department: 2813)
Electrical connectors
Contact comprising cutter
Resiliently biased
Reexamination Certificate
active
06561839
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of integrated circuits and notably to the formation of shallow voluminal isolating regions or isolating lateral regions.
2. Description of Related Art
Such shallow voluminal isolating regions serve to realize electrical isolation in the lateral direction between the active regions that contain the active elements, being mainly CMOS transistors, of an integrated circuit realized on a semiconductor substrate.
Nowadays such isolating regions are formed in principle by chemical etching of the desired parts of the surface of the semiconductor substrate so as to form grooves of a desired depth. Subsequently, after a given number of steps for preparation and cleaning, an electrically isolating oxide is deposited on the entire surface of the structure so that the groove is completely filled. The excess oxide material is subsequently removed again by means of a chemical etching process.
An example of the formation of such isolating regions in conformity with prior art will be described in detail hereinafter.
First stack of layers is formed on the surface of the substrate of semiconductor material (wafer). First of all (i) a sacrificial oxide layer or buffer layer, commonly referred to as a “padox” by those skilled in the art, is formed on the upper surface of the substrate. (ii) A second layer, referred to hereinafter as a “hard mask” (for example, Si
3
N
4
) in view of its ultimate function, is subsequently formed by chemical deposition in the vapor phase (CVD). (iii) A resin mask which defines the dimensions of the future isolating region is subsequently formed on the hard mask layer. (iv) The hard mask layer (silicon nitride) and the buffer layer (silicon oxide) are removed through the opening of the resin mask so as to expose the upper surface of the substrate. (v) The substrate is then subjected to chemical etching in depth in order to form the groove. When the desired groove depth is reached, (vi) the resin layer is removed.
(vii) In the course of a later treatment that is known to those skilled in the art as “exposure of the padox”, the buffer layer (silicon oxide), still being sandwiched between the substrate and the hard mask layer (silicon nitride) at this stage of the process, is subjected to lateral etching so as to obtain a cavity at a desired lateral distance. (viii) Before the groove is filled, it is oxidized.
(ix) The groove is subsequently filled with silicon dioxide and then (x) with TEOS (tetraorthosilicate of ethyl) oxide or with an oxide of the type HDP (high density plasma) before (xi) starting with densification annealing in a furnace or an apparatus of the type RTP (rapid thermal process).
(xii) A block of resin is thus formed on the oxide TEOS above the groove.
(xiii) Using the resin block as a mask, chemical etching is performed on the structure, after which (xiv) the resin block is removed and (xv) chemical-mechanical polishing (CMP) is performed until the hard mask layer (silicon nitride) becomes exposed.
(xvi) Finally, the hard mask layer outside the grooves is eliminated by chemical etching.
Such a prior art process is not very practical in that it is necessary to carry out a large number of steps, notably chemical etching operations in a humid environment, and some of these steps are difficult to master. Moreover, it has been found that it is difficult to achieve a reproducible uniformity for the groove structure in the various areas on the substrate and in the various substrates in different batches.
BRIEF SUMMARY OF THE INVENTION
It is the object of the invention to provide a solution to these problems.
One of the objects of the present invention is to reduce the number of steps, and hence the manufacturing costs, that has to be carried out for the formation of a shallow isolating region. Another object is to realize a process that can be mastered better and yields a better reproducible uniformity for the structure of the isolating region.
Therefore, the invention proposes a process for manufacturing an integrated circuit which includes a step for forming an isolating region within a voluminal part of a substrate. In conformity with a general characteristic aspect of the invention, the formation of the isolating region includes an ion implantation in said voluminal part, followed by annealing of said implanted voluminal part of the substrate.
These two steps in accordance with the invention replace the steps (iv) and (xiv) of the prior art process described above.
It is to be noted that the annealing leads to the formation of oxide in the implanted zone. Moreover, because use is made of a monocrystalline substrate, the implanted zone will be enclosed by a monocrystalline silicon network which facilitates the formation and the recrystallization of the oxide.
Moreover, the two steps in accordance with the invention not only give rise to recrystallization of the oxide, but also to regeneration of the silicon network at the interface between the silicon (active zone) and the oxide (isolating region).
In one version the ions implanted in the voluminal part of the substrate are oxygen ions. The annealing operation in particular can be performed at a high temperature.
In conformity with one version of the invention, the formation of the isolating region includes the steps of:
forming a stack of layers, including a buffer layer and a masking layer, on a substrate,
providing the masking layer with an opening whose dimensions define those of said isolating region.
This opening thus exposes a part of the buffer layer. The implantation of ions in the substrate is carried out through the buffer layer.
Various versions of the invention can be used for advantageously completing the formation of an isolating region by implantation and annealing.
Thus, in conformity with one version the following steps may be carried out after the implantation:
1a) covering the masking layer, the lateral walls of the opening and the exposed part of the buffer layer within the opening with an oxide cover layer;
1b) chemical mechanical polishing of the upper surface of the structure obtained in the step 1a), and
1c) selectively removing the masking layer. This leaves a residue of the initial oxide layer applied during the step 1a).
According to this version, the oxide cover layer makes it possible to realize an additional oxide thickness which enables the consumption of oxide in the isolating region to be minimized during the selective etching; it also minimizes the risk of formation of a depression (step) in the isolating region relative to the active zone which would have an adverse effect on the operation of MOS devices.
In another version the covering by means of the oxide cover layer can be performed prior to implantation. In that case the implantation takes place through the oxide cover layer and through the buffer layer. The oxide cover layer then serves to minimize the overall consumption of oxide during the implantation which is due to the oxide erosion phenomenon (sputtering) that inevitably occurs during any implantation. This oxide layer will subsequently also serve as indicated for protection during the selective etching.
In another version the following steps may be carried out:
2a) covering, by selective oxidation, the lateral wall of the opening and the exposed part of the buffer layer within the opening by means of an oxide cover layer, and
2b) selectively etching the masking layer. This again leaves a residue of the initial oxide layer on the previously exposed part of the buffer layer.
Moreover, according to this version, and analogously to that explained above, the oxide cover layer obtained by selective oxidation also enables an additional oxide thickness to be obtained, thus enabling a minimization of the oxide consumption of the isolating region as well as of the risk of forming a depression (step) of the isolating region relative to the active zone.
In another version the covering by the oxide cover layer realized by selective oxidation may also be performed prio
Arnaud Franck
De Coster Walter Jan August
Inard Alain
Lunenborg Meindert Martin
Blum David S
Jr. Carl Whitehead
Koninklijke Philips Electronics , N.V.
Waxler Aaron
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