Process for forming self-aligned contact of semiconductor...

Details Process for forming self-aligned contact of semiconductor... Process for forming self-aligned contact of semiconductor...

1999-09-27

2001-04-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S197000, C438S199000, C438S230000, C438S233000, C438S622000, C438S637000, C438S666000, C438S696000, C438S634000, C438S749000

Reexamination Certificate

active

06218275

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a process for forming a contact structure of a semiconductor device, and more particularly to a process for forming a self-aligned contact hole on a metal-oxide-semiconductor (MOS) transistor.
BACKGROUND OF THE INVENTION
The size of an integrated circuit is getting smaller and smaller, but the requirement of the integration level is generally raised. In a process for manufacturing a semiconductor device, the accuracy of a photolithographic process is limited by the resolution. It is not easy to precisely define a contact structure of the semiconductor device when the device is small. Therefore, a self-aligned contact (SAC) process is developed and widely used in the semiconductor manufacturing process.
Please refer to FIGS.
1
(
a
)~(
h
) which schematically show the steps for manufacturing a contact plug between two MOS transistors by the self-aligned contact process of the prior art. Referring to FIG.
1
(
a
), a plurality of gates of the MOS transistor is formed on the substrate
10
. Each gate includes a polycide layer
12
and a first silicon nitride layer
13
formed on the polycide layer
12
. A first oxide layer
11
is formed on the substrate
10
by a rapid thermal process (RTP). Referring to FIG.
1
(
b
), a second silicon nitride layer
14
is formed over the first oxide layer
11
and the gates. The second silicon nitride layer
14
is formed by low pressure chemical vapor deposition (LPCVD). Referring to
FIG. 1
(
c
), portions of the second silicon nitride layer
14
and the first oxide layer
11
are removed by an etching process. After the residual portion of the first oxide layer
11
is removed by an acid solution, spacers
15
are formed on sidewalls of the gates. The acid solution is usually hydrofluoric acid.
Please refer to FIGS.
1
(
d
)~(
h
) which shows the steps of the self-aligned contact process. In FIG.
1
(
d
), a first dielectric layer
16
is formed on the gates and the spacers
15
by chemical vapor deposition (CVD). The dielectric layer
16
can be a silicon nitride layer or a silicon oxynitride layer. In FIG.
1
(
e
), a second oxide layer
17
is formed over the dielectric layer
16
by another CVD process. Thereafter, a photoresist layer
18
is formed on the second oxide layer
17
. The photoresist layer is patterned by a photolithographic process and a portion of the second oxide layer
19
will be exposed as shown in FIG.
1
(
f
). A contact hole
20
is formed after the exposed portion of the second oxide layer
19
, and portions of the first dielectric layer
16
and spacers
15
are removed by an anisotropic etching process. The residual photoresist layer is removed by SPM (Sulfuric acid and hydrogen peroxide). A polysilicon layer
21
is formed between two gates by a CVD process. Finally, a polysilicon contact plug
21
is formed for connecting the source region and the drain region (not shown) of the MOS transistor.
The spacers
15
are made of silicon nitride, the first dielectric layer
16
is a silicon nitride layer or a silicon oxynitride layer, and the second oxide layer
17
is a silicon oxide layer. The etching selectivity ratio of silicon oxide to silicon nitride or silicon oxynitride is relatively high. Therefore, the first silicon nitride layer
13
of the gate, the spacers
15
, and the first dielectric layer
16
will not be totally removed by the etching process for removing the second oxide layer
17
. A short circuit between the polysilicon contact plug
21
and the polycide layer
12
of the gate will not occur. In addition, the opening of the photoresist layer
18
is not necessary to be precisely aligned between two gates of the MOS transistor because of the high etching selectivity ratio. Moreover, the width B of the opening
19
can be greater than the distance A between two gates.
Referring to FIG.
1
(
h
), the length L is the shortest distance between the polysilicon contact plug
21
and the polycide layer
12
. When the size of the semiconductor device is reduced, the length L is also reduced. However, the resolution of the photolithographic process is limited, so that the width B of the opening
19
can not be reduced. Therefore, the width B may be much greater than the distance A between two gates, and the length L will become very small after the etching process. However, a short circuit will be occurred between the polysilicon contact plug
21
and the polycide layer
12
if the length L is too small. Therefore, it is desirable to develop a method for solving the problems encountered with the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process for forming a contact structure of a semiconductor device.
Another object of the present invention is to provide a self-aligned contact process for forming a self-aligned contact hole on a MOS transistor.
According to the present invention, the process for forming a contact structure of a semiconductor device includes steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates. The process further includes steps of (e) removing a portion of the first dielectric layer and the first oxide layer to expose a portion of the substrate by using the first spacers as a mask for forming second spacers alongside each of the gates, (f) forming a second dielectric layer over the exposed portion of the substrate, the second spacers, and the gates, (g) forming a third dielectric layer over the second dielectric layer, and (h) executing a photolithographic and etching process on the third dielectric layer to form the contact structure between the gates on the substrate.
The semiconductor device includes a plurality of metal oxide semiconductor (MOS) transistors. Each of the MOS transistors includes a source, a drain, and the gate. Each of the gates includes a conducting layer and a silicon nitride layer formed on the conducting layer. The conducting layer is a polycide layer.
After the step (h), the process further includes a step (i) of depositing a polysilicon layer over the third dielectric layer and the contact structure for forming a polysilicon contact plug connected with one of the source and the drain of the MOS transistor. Certainly, the first dielectric layer can be a silicon nitride layer and the second oxide layer can be a silicon oxide layer. The second dielectric layer is one selected from a silicon nitride layer and a silicon oxynitride layer, and the third dielectric layer can be a silicon oxide layer.
According to the present invention, the steps (b) and (c) are executed by low pressure chemical vapor deposition (LPCVD). The steps (d) and (e) are respectively executed by an anisotropic etching process. The step (e) further includes a step of removing the first spacers and a portion of the first oxide layer to expose a portion of substrate by using an acid solution after the second spacers are formed. The acid solution of step (e) is one selected from hydrofluoric acid (HF) and sulfuric acid (H
2
SO
4
). In addition, the step (f) is executed by low pressure chemical vapor deposition (LPCVD), and the step (g) is executed by chemical vapor deposition (CVD).
According to the present invention, the step (h) includes steps of (h1) forming a photoresist layer on the third dielectric layer, (h2) removing a portion of the photoresist layer to expose a portion of the third dielectric layer, (h3) removing the exposed portion of the third dielectric layer, a portion of the second spacers, and a portion of the second dielectric layer not covered by the photoresist layer to expose a portion of the substrate, and (h4) removing the photoresist layer by using an acid solution for forming the contact structure between the gates. The width of the exposed portion of the third dielect

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