Process for forming polycrystalline thin film transistor...

Details Process for forming polycrystalline thin film transistor... Process for forming polycrystalline thin film transistor...

2001-03-19

2002-04-02

Christiansen, Keith (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S404000, C438S424000, C438S153000, C438S154000

Reexamination Certificate

active

06365444

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for forming a thin film transistor-liquid crystal display (TFT-LCD), and more particularly to a process for forming a complementary poly-silicon TFT-LCD.
BACKGROUND OF THE INVENTION
In the conventional process for fabricating TFT-LCD (thin film transistor liquid crystal display), the semiconductor materials such as the channel layer and the source/drain layer of the active matrix switch are usually made of intrinsic amorphous silicon and highly doped amorphous silicon respectively. Due to the low conductivity of the amorphous silicon material, the driving current ability of the amorphous silicon material can not meet the requirement of the LCD peripheral driving circuit. Therefore, the semiconductor material layer made of the intrinsic poly-silicon and highly doped poly-silicon has better conductivity and is easily to be assembled with the LCD device. The conventional process for TFT-LCD properly is complicated, hence, it is better way to achieve the TFTs and the LCD peripheral driving circuit at the same time.
The TFTs and the LCD peripheral driving circuit are principally composed of the P-type and the N-type poly-silicon TFTs. As shown in FIGS.
1
(
a
) to
1
(
f
), the conventional steps for forming a complementary poly-silicon TFT including the P-type and N-type poly-silicon TFT and the peripheral driving circuit by employing eight masking and patterning process steps.
In view of FIG.
1
(
a
), a silicon oxide (SiOx) barrier layer
11
and a poly-silicon layer on a glass substrate
10
are formed and a first masking and patterning procedure is performed to define a ploy-silicon channel layer
12
on the poly-silicon layer.
In view of FIG.
1
(
b
), a gate insulation material structure and a gate conductive material structure are successively formed and a second masking and patterning procedure is performed to define a gate insulation layer
13
and a gate conductive layer
14
respectively.
Referring to FIG.
1
(
c
), a third masking and patterning procedure is proceeded and then an N-type ion-implanting procedure is performed on the exposed portions of a poly-silicon channel layer
12
uncovered with a photoresist
15
for forming a source/drain region
121
of an N-type poly-silicon TFT.
Referring to FIG.
1
(
d
), a fourth masking and patterning procedure is proceeded and then a P-type ion-implanting procedure is performed on the exposed portions of a poly-silicon channel layer
12
uncovered with a photoresist
16
for forming a source/drain region
122
of a P-type poly-silicon TFT.
As for FIG.
1
(
e
), a silicon oxide interlayer
17
is formed and a fifth masking and patterning procedure is performed to define a contact hole
18
.
With regard to FIG.
1
(
f
), a metal conductive layer is formed and a sixth masking and patterning procedure is performed to define a source/drain conductive layer
19
. Subsequently, a seventh and an eighth masking and patterning procedures are proceeded to define a passivation layer and a transparent electrode layer (not shown in Figure) respectively.
Thus, the above-mentioned conventional process has disadvantages of high manufacturing cost and time-consuming by using eight masking and patterning procedures. It is therefore tried by the applicant to deal with the above situation encountered by the prior art.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a process for forming a poly-silicon TFT-LCD with reduced masking and patterning steps.
It is another object of the present invention to provide a process for forming a poly-silicon TFT-LCD to reduce the manufacturing cost and the procedure time.
According to the present invention, there is provided the process for forming a thin film transistor (TFT) liquid crystal display (LCD). The process includes steps of providing a substrate made of an insulating material, forming a first conductive layer on the substrate, performing a first masking and patterning procedure to define a gate conductive region on the substrate, successively forming an insulation layer, an amorphous semiconductor channel layer, a catalytic layer and a doped semiconductor layer on the substrate, performing a second masking and patterning procedure to remove portions of the doped semiconductor layer and the catalytic layer to define an electrode region, performing a thermal treatment for the substrate to respectively convert the electrode region and the amorphous semiconductor channel layer into a source/drain region and a crystalline semiconductor channel layer by the catalytic layer, forming a second conductive layer on the substrate and performing a third masking and patterning procedure to define data lines, forming a passivation layer and performing a fourth masking and patterning procedure to remove portions of the passivation for forming a contact hole accessible to the data line, and forming a transparent electrode layer and performing a fifth masking and patterning procedure to define a transparent pixel electrode region, thereby forming the thin film transistor.
Preferably, the first conductive layer is a gate conductive layer.
Preferably, the amorphous semiconductor channel layer is formed of intrinsic amorphous silicon and the doped semiconductor layer is formed of highly doped amorphous silicon.
Preferably, the catalytic layer is formed of a catalytic metal.
Preferably the catalytic metal is formed of Nickel.
Preferably the thermal treatment is an annealing procedure for heating 4 hours at 550° C. under one of a hydrogen atmosphere and an inert gas atmosphere.
According to a further aspect of the present invention, there is provided a process for forming a complementary TFT LCD. The process includes steps of providing a substrate made of an insulating material, forming a first conductive layer on the substrate, performing a first masking and patterning procedure to define two gate conductive regions on the substrate, successively forming an insulation layer, an amorphous semiconductor channel layer, a catalytic layer, an N-type doped amorphous semiconductor layer on the substrate, performing a second masking and patterning procedure to remove portions of the N-type doped amorphous semiconductor layer and the catalytic layer to define a first electrode region and a second electrode region, forming a photoresist layer and performing a third masking and patterning procedure to expose the second electrode region, performing a P-type doping procedure to convert the materials of the second electrode region into a P-type doped amorphous semiconductor, performing a thermal treatment for the substrate to convert the first electrode region and the second electrode region and the amorphous semiconductor channel layer into a first source/drain region, a second source/drain region and a crystalline semiconductor layer by the catalytic layer, forming a second conductive layer and performing a fourth masking and patterning procedure to define data lines, forming a passivation layer and performing a fifth masking and patterning procedure to remove portions of the passivation layer to form a contact hole accessible to the data lines, forming a transparent electrode layer and performing a sixth masking and patterning procedure to form a transparent pixel region, thereby forming the complementary TFT.
According to a still aspect of the present invention, there is provided a process for forming a complementary TFT-LCD. The process includes steps of providing a substrate made of an insulating material, forming a first conductive layer on the substrate, performing a first masking and patterning procedure to define two gate conductive regions on the substrate, successively forming an insulation layer, an amorphous semiconductor channel layer, a catalytic layer, a P-type doped amorphous semiconductor layer on the substrate, performing a second masking and patterning procedure to remove portions of the P-type doped amorphous semiconductor layer and the catalytic layer to define a first electrode region and a second electro

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