Process for forming planar chip-level wiring

Details Process for forming planar chip-level wiring Process for forming planar chip-level wiring

1986-03-21

1987-08-25

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156653, 156656, 156657, 1566591, 1566611, 156668, 156904, 20419232, 357 65, 357 67, 357 71, 430314, 430315, 430317, 430318, 437228, B44C 122, C23F 102, C03C 1500, B29C 3700

Patent

active

046891137

ABSTRACT:
Disclosed is a process of forming high density, planar, single- or multi-level wiring for a semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring.
When only narrow wiring is desired, a single photoresist layer is substituted for the dual photoresist sacrificial layer.

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IBM Technical Disclosure Bulletin, vol. 24, No. 9, Feb. 1982, pp. 4839-4840, by A. J. Hoeg, Jr. et al., "Metal Lift-Off Process with a Self-Aligned Insulation Planarization".
IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mar. 1983, pp. 5309-5314, by G. T. Chiu et al, "Process for Multilayer Metal Technology".
1982 IEEE IEDM 82--pp. 391-394, by B. J. Lin, "Multi-Layer Resist Systems as a Means to Submicron Optical Lithography".

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