Process for forming multilevel interconnection structure

Details Process for forming multilevel interconnection structure Process for forming multilevel interconnection structure

1999-04-27

2000-03-14

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438629, 438633, 438637, 438687, 438714, H01L 2128, H01L 21302

Patent

active

060372508

ABSTRACT:
A method for forming a multi-level copper interconnection structure includes the steps of etching an interlayer dielectric film using a photoresist mask to form an opening for exposing a copper interconnect, and removing the photoresist mask by a plasma ashing at a substrate temperature lower than 150.degree. C. and a RF power not higher than 0.7 watts/cm.sup.2. The plasma ashing prevents formation of a copper oxide film on the surface of the copper interconnect thereby reducing the contact resistance between the via plug and the copper interconnect.

REFERENCES:
patent: 5294292 (1994-03-01), Yamashita et al.
patent: 5561082 (1996-10-01), Matsuo et al.
patent: 5744376 (1998-04-01), Chan et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5891799 (1999-04-01), Tsui
patent: 5909637 (1999-06-01), Charneski et al.

Affiliated with

Also associated with

Rating

Process for forming multilevel interconnection structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming multilevel interconnection structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming multilevel interconnection structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-168866