Process for forming multi-layer interconnections

Details Process for forming multi-layer interconnections Process for forming multi-layer interconnections

1984-11-28

1986-04-15

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29591, 156644, 156646, 156657, 1566591, 204192EC, 204192E, 357 71, 427 90, 427 91, 427 93, B44C 122, C23F 102, H01L 2348, H01L 2946

Patent

active

045825637

ABSTRACT:
First conductive members are buried in first holes formed in a first insulating film to connect the second interconnection layers, formed through first and second insulating films, to a semiconductor substrate. Second conductive members are buried in second holes formed to be positioned on the first holes of the second insulating film. Thus, the reliability of a semiconductor device of a multi-layer interconnection structure is improved, and the integration thereof is improved.

REFERENCES:
patent: 4307179 (1981-12-01), Chang et al.
patent: 4330931 (1982-05-01), Liu
patent: 4367119 (1983-01-01), Logan et al.
patent: 4520041 (1985-05-01), Aoyama et al.

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