Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-03-01
2003-07-01
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S686000, C257S796000, C257S737000, C438S109000
Reexamination Certificate
active
06586836
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and processes for packaging microelectronic dice. In particular, the present invention relates to a packaging technology that fabricates build-up layers on an encapsulated microelectronic die and on the encapsulation material that partially covers the microelectronic die.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a “chip scale packaging” or “CSP”.
As shown in
FIG. 8
, true CSP would involve fabricating build-up layers directly on an active surface
204
of a microelectronic die
202
. The build-up layers may include a dielectric layer
206
disposed on the microelectronic die active surface
204
. Conductive traces
208
may be formed on the dielectric layer
206
, wherein a portion of each conductive trace
208
contacts at least one contact
212
on the microelectronic die active surface
204
. External contacts, such as solder balls or conductive pins for contact with an external component (not shown), may be fabricated to electrically contact at least one conductive trace
208
.
FIG. 8
illustrates the external contacts as solder balls
214
where are surrounded by a solder mask material
216
on the dielectric layer
206
. However in such true CSP, the surface area provided by the microelectronic die active surface
204
generally does not provide enough surface for all of the external contacts needed to contact the external component (not shown).
Additional surface area can be provided through the use of an interposer, such a substrate (substantially rigid material) or a flex component (substantially flexible material).
FIG. 9
illustrates a substrate interposer
222
having a microelectronic die
224
attached to and in electrical contact with a first surface
226
of the substrate interposer
222
through small solder balls
228
. The small solder balls
228
extend between contacts
232
on the microelectronic die
224
and conductive traces
234
on the substrate interposer first surface
226
. The conductive traces
234
are in discrete electrical contact with bond pads
236
on a second surface
238
of the substrate interposer
222
through vias
242
that extend through the substrate interposer
222
. External contacts are formed on the bond pads
236
(shown as solder balls
244
).
The use of the substrate interposer
222
requires number of processing steps. These processing steps increase the cost of the package. Additionally, even the use of the small solder balls
228
presents crowding problems which can result in shorting between the small solder balls
228
and can present difficulties in inserting underfilling between the microelectronic die
224
and the substrate interposer
222
to prevent contamination.
FIG. 10
illustrates a flex component interposer
252
wherein an active surface
254
of a microelectronic die
256
is attached to a first surface
258
of the flex component interposer
252
with a layer of adhesive
262
. The microelectronic die
256
is encapsulated in an encapsulation material
264
. Openings are formed in the flex component interposer
252
by laser abalation through the flex component interposer
252
to contacts
266
on the microelectronic die active surface
254
and to selected metal pads
268
residing within the flex component interposer
252
. A conductive material layer is formed over a second surface
272
of the flex component interposer
252
and in the openings. The conductive material layer is patterned with standard photomask/etch processes to form conductive vias
274
and conductive traces
276
. External contacts are formed on the conductive traces
276
(shown as solder balls
278
surrounded by a solder mask material
282
proximate the conductive traces
276
).
The use of a flex component interposer
252
requires gluing material layers which form the flex component interposer
252
and requires gluing the flex component interposer
252
to the microelectronic die
256
. These gluing processes are relatively difficult and increase the cost of the package.
Therefore, it would be advantageous to develop new apparatus and techniques to provide additional surface area to form traces for use in CSP applications, while utilizing commercially available, widely practiced semiconductor fabrication techniques.
REFERENCES:
patent: 5280192 (1994-01-01), Kryzaniwsky
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5422513 (1995-06-01), Marcinkiewicz et al.
patent: 5463253 (1995-10-01), Waki et al.
patent: 5491612 (1996-02-01), Nicewarner, Jr.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5508565 (1996-04-01), Hatakeyama et al.
patent: 5527741 (1996-06-01), Cole et al.
patent: 5530292 (1996-06-01), Waki et al.
patent: 5703400 (1997-12-01), Wojnarowski et al.
patent: 5745984 (1998-05-01), Cole, Jr. et al.
patent: 5798564 (1998-08-01), Eng et al.
patent: 5838061 (1998-11-01), Kim
patent: 5861666 (1999-01-01), Bellaar
patent: 5883426 (1999-03-01), Tokuno et al.
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6002167 (1999-12-01), Hatano et al.
patent: 6013948 (2000-01-01), Akram et al.
patent: 6072700 (2000-06-01), Nam
patent: 6084294 (2000-07-01), Tomita
patent: 6087718 (2000-07-01), Cho
patent: 6087719 (2000-07-01), Tsunashima
patent: 6091142 (2000-07-01), Lee
patent: 6118184 (2000-09-01), Ishio et al.
patent: 6133637 (2000-10-01), Hikita et al.
patent: 6137162 (2000-10-01), Park et al.
patent: 6137163 (2000-10-01), Kim et al.
patent: 11045955 (1999-02-01), None
patent: 11312868 (1999-11-01), None
Ma Qing
Mu Xiao-Chun
Towle Steve
Vu Quat
Cruz Lourdes
Cuneo Kamand
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Process for forming microelectronic packages and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for forming microelectronic packages and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming microelectronic packages and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3059038