Process for forming low-reactance interconnections on semiconduc

Details Process for forming low-reactance interconnections on semiconduc Process for forming low-reactance interconnections on semiconduc

1979-12-28

1981-09-15

Smith, John D.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

204 15, 427 89, 427 96, 427 57, 430315, 430329, H01L 21288

Patent

active

042898463

ABSTRACT:
Several methods are disclosed for forming an air gap between crossing thin film conductors utilized to interconnect electronic components on a substrate. Each of the methods involves the use of photolithographic techniques to form overpassing conductors on a support material covering the overpassed conductors, followed by removal of the support material. Both deposition and plating techniques are described for forming the overpassing conductors.

REFERENCES:
patent: 3681134 (1972-08-01), Nathanson et al.
patent: 4016050 (1977-04-01), Lesh et al.
patent: 4054484 (1977-10-01), Lesh
patent: 4141055 (1979-02-01), Berry et al.
patent: 4200975 (1980-05-01), Debiec et al.
Semiconductor International, "Raytheon's `Via Hole ` Technology Yields Very Stable GaAs FETs", p. 14, Oct. 1977.

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