Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1998-10-06
2001-10-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S787000, C438S799000, C438S141000
Reexamination Certificate
active
06309952
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to the manufacture of high-voltage semiconductor integrated circuits, and is particularly directed to a new and improved process for forming a junction termination extension (JTE) oxide that enjoys reduced total oxide charge (Qox) and SiO
2
—Si interface trap density (Dit) parameters, thereby offering improved high voltage edge stability.
BACKGROUND OF THE INVENTION
High-voltage discrete and integrated circuit devices, which are currently employed in a wide variety of electrical and electronic circuit architectures, are subject to excessive electric field intensity created in the vicinity of a reverse-biased PN junction. One particularly effective mechanism to deal with this problem has been to use a junction termination extension (JTE), as a barrier against the effects of the electric field. In a typical architecture, the JTE device is passivated by a relatively thick bulk oxide layer that is formed by the process sequence shown in
FIG. 1
, respective steps of which yield a device structure shown in the associated cross-sectional diagrams of
FIGS. 2A-2F
.
More particularly, as shown at step
101
, the conventional process begins by exposing the top surface of a semiconductor (silicon) substrate
1
, shown in
FIG. 2A
, to a ‘wet’ or steam ambient, so as to rapidly grow a relatively thick ubiquitous oxide layer
2
, that is to serve as part of the bulk JTE oxide. As shown at step
103
and
FIG. 2B
, the oxide layer
2
is then patterned, etched and cleaned/rinsed to open a plurality of implant apertures
3
, which expose corresponding (JTE dopant-implant) surface portions
4
in the top surface of substrate
1
.
In step
105
, conductivity type determining impurities
5
are implanted through the implant apertures
3
of the oxide layer
2
, forming a plurality of JTE surface regions shown at
6
in FIG.
2
C. This implant step introduces unwanted near-surface pockets of crystalline damage
7
in the vicinity of the top surface of the silicon substrate. In order to remove this crystalline damage and prevent stacking fault formation, at step
107
, a wet or stream screen oxide layer
8
is rapidly grown directly on the JTE surface regions
6
, as shown in FIG.
2
D. Unfortunately, because the oxide layer
8
is grown rapidly and directly upon the implanted surface of the silicon, it is of relatively poor quality, and can be expected to negatively impact the quality of any subsequently formed oxide.
Following formation of the screen oxide layer
8
, the device is subjected to a dopant drive-in step
109
, which causes the dopant of the implanted regions
6
to diffuse into the surrounding substrate, and essentially define the JTE structure, as shown at
6
′ in FIG.
2
E. Although some additional dopant diffusion will occur during subsequent oxidation,.the bulk of the dopant drive-in is completed in this step. The JTE oxide process is completed by performing a further rapid steam or wet oxidation step
111
, which fills in the implant apertures
3
with oxide
9
and results in the JTE structure shown in FIG.
2
F.
Because each of the oxide layers formed in the process of
FIGS. 1 and 2
, particularly those overlying the implanted regions, are grown rapidly in a wet or stream atmosphere, they are of relatively low density. As a result they facilitate segregation or out-diffusion of dopants into the oxide, and reduce the quality of any oxide grown thereon. This has the unwanted effect of allowing the total oxide charge (Qox) and Sio
2
—Si interface trap density (Dit) to increase, which degrades high voltage stability.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above-referenced shortcomings of conventional JTE oxide formation are effectively obviated by employing precursor densified thin oxide layers to improve the quality of subsequently formed thicker oxide layers, and performing multiple anneals in a dry or non-oxidizing atmosphere to remove implant damage and to set finalized geometry parameters. The use of such an atmosphere for post JTE oxidation annealing substantially lowers Qox and Dit.
In order to ensure precise control of subsequent oxide formation, a relatively thin and dense precursor oxide layer is ubiquitously grown on the surface of a silicon substrate in a dry oxygen ambient. The thickness of the oxide layer is increased in a steam or wet oxygen atmosphere, causing the growth of a relatively thick silicon dioxide layer. Because the thin precursor oxide layer is highly densified, it increases the density and quality of the thick oxide layer.
A post-oxidation anneal is then performed in a dry ambient or non-oxidizing atmosphere, which substantially reduces Qox and Dit. The oxide then masked and etched to form a plurality of dopant implant apertures in the oxide layer. JTE dopants are then implanted through the implant apertures of the oxide layer, forming a plurality of conductivity-modifying semiconductor JTE regions that extend to a prescribed implant depth from the top surface of the silicon substrate.
In order to remove near surface crystalline damage caused by the implant, the substrate is annealed in a non-oxidizing or inert gas ambient. The non-oxidizing atmosphere of the annealing step prevents oxidation of the top surface of the substrate from which the JTE regions extend, and thereby avoids negatively impacting subsequent oxide formation. A dry oxide ambient cannot be used to anneal out the crystalline damage during this step, since formation of a highly dense oxide layer may cause the formation of oxidation-induced stacking faults. The JTE dopants are then partially driven away from the near-surface portions into adjoining material of the substrate, to prevent segregation of the dopant into the oxide that will be subsequently grown.
A relatively thin and highly densified bulk oxide precursor layer is then grown on the exposed JTE dopant-implanted surface portions of the substrate to ensure precise control of subsequent oxide formation. The bulk of the JTE oxide is then formed in a steam or wet oxygen atmosphere.
After the bulk oxide has been grown to its desired thickness, the substrate is annealed in a non-oxidizing or inert gas ambient, to cause a further drive-in of the JTE dopants. The dry or non-oxidizing atmosphere of the post JTE oxidation annealing step substantially lowers Qox and Dit. The reduction in Qox and Dit (and thereby the extent to which high voltage edge stability is improved) may be determined by carrying out conventional capacitance-voltage and associated electrical parameter measurements, such as those commonly employed for MOS capacitor structures.
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Ridley Rodney S.
Trost Jason R.
Webb Raymond J.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Fairchild Semiconductor Corporation
Rocchegiani Renzo N.
Smith Matthew
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