Process for forming high dielectric constant gate dielectric...

Details Process for forming high dielectric constant gate dielectric... Process for forming high dielectric constant gate dielectric...

2001-10-19

2003-01-28

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S216000, C438S240000, C438S261000, C438S287000, C438S783000

Reexamination Certificate

active

06511925

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for forming integrated circuit structures. More particularly, this invention relates to a process for forming a high dielectric constant gate dielectric for an MOS transistor of an integrated circuit structure.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, the dimensions of active devices have become smaller and smaller, as well as the dimensions of the lines between the active devices. The shrinking of the field-effect device channel length in an active device requires an increase in the capacitance of the gate electrode in order to achieve desired performance. However, when the gate dielectric is SiO
2
, there are difficulties associated with decreasing the gate oxide thickness to achieve such desired increase in capacitance. Such difficulties include increased leakage across the thin silicon oxide dielectric, when the oxide thickness is reduced to 1 nanometer (nm) or less, as well as diffusion of dopant from the gate electrode through the thin gate oxide to the channel region of the silicon substrate below the thin gate oxide dielectric.
An alternate approach has been to form a high dielectric constant (high-k) gate dielectric by depositing high-k dielectrics such as ZrO
2
, HfO
2
, and mixtures of either or both with SiO
2
. One difficulty with this approach, generally, is that these materials are mismatched to the silicon lattice. The consequence of this mismatch is formation of interface states, a very undesirable feature. There are also questions involving the stability of these high-k materials to mechanical and temperature induced stresses. An additional problem with the use of such high k dielectric material is their sensitivity to formation temperature to avoid crystallinity (which could effect leakage and dopant migration).
Attempts to address these issues have led to growing a very thin layer of SiO
2
, to avoid formation of interface states due to lattice mismatch, and then depositing a layer of the high-k dielectric material over the thin layer of SiO
2
. However, since the reciprocal of the total capacitance of the gate dielectric is the sum of the reciprocals of the capacitance of the thin SiO
2
layer plus the capacitance of the high-k layer, the presence of the thin SiO
2
layer reduces the effectiveness of the high-k dielectric layer.
Exposure of a silicon oxide surface to a low energy nitrogen plasma to insert nitrogen atoms into silicon oxide is taught in Puchner et al. U.S. Pat. No. 6,156,620; Aronowitz et al. U.S. patent application Ser. No. 09/464,297, filed Dec. 15, 1999; and Aronowitz et al. U.S. patent application Ser. No. 09/521,312, filed Mar. 9, 2000; all assigned to the assignee of this invention and the subject matter of each of which is hereby incorporated herein by reference.
Kaushik et al. U.S. Pat. No. 6,184,072 B1 proposes to first form a layer of silicon oxide over a silicon substrate and then to form a metal layer over the silicon oxide layer, using a metal capable of forming a high-k oxide layer when ions of such metal are diffused into the silicon oxide layer. A diffusion step is then carried out wherein the structure is heated to about 400° C.-800° C. to diffuse metal ions from the metal layer into the silicon oxide layer to form a high-k gate dielectric. The Kaushik et al. patent further teaches implanting or diffusing metal into a silicon substrate followed by a thermal anneal in a oxygen ambient atmosphere which may also contain nitrogen or steam. At the completion of the annealing step a high-k dielectric layer is formed on top of the silicon substrate.
However, it would be preferable to form a high-k dielectric layer suitable for use as a gate dielectric using, as a precursor, a conventional silicon oxide which is then modified to form the desired high-k gate dielectric.
SUMMARY OF THE INVENTION
In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.


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