Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-10-31
1999-03-30
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438624, 438976, H01L 2144
Patent
active
058888977
ABSTRACT:
A method of forming an integrated structure that comprises a self-aligned via/contact and metal line is described. The via/contact is formed out of part of a first spacer made of a first dielectric and surrounded by a second dielectric in a first sandwich structure. The metal line is formed out of a second spacer made of the first dielectric and surrounded by the second dielectric in a second sandwich structure. The second sandwich structure is disposed over the first sandwich structure. At the point of contact between the first and second spacer, an angle of 90.degree. exists in a preferred embodiment. The via/contact and metal line form a self-aligned integrated structure that is created in one etch step. The integrated structure is subsequently filled with a conductive material.
REFERENCES:
patent: 4883767 (1989-11-01), Gray et al.
patent: 5063169 (1991-11-01), De Bruin et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5187121 (1993-02-01), Cote et al.
patent: 5219787 (1993-06-01), Carey et al.
patent: 5270236 (1993-12-01), Rosner
patent: 5286674 (1994-02-01), Roth et al.
patent: 5319247 (1994-06-01), Matsuura
patent: 5352630 (1994-10-01), Kim et al.
patent: 5382545 (1995-01-01), Hong
patent: 5461004 (1995-10-01), Kim
patent: 5714039 (1998-02-01), Beilstein, Jr. et al.
IBM Technical Disclosure Bulletin, "Method for Forming Via Hole Formation" vol. 34, 10A, Mar. 1992, pp. 219-220.
IBM Technical Disclosure Bulletin, "Self-Aligned, Borderless Polysilicon Contacts Using Polysilicon Pillars", vol. 35, No. 2, Jul. 1992, pp. 480-483.
T. Fukase,et al., "A Margin-Free Contact Process Using An A1.sub.2 O.sub.3 Etch-Stop Layer For High Density Devices", IEEE, Apr. 1992, pp. 33.3.1-33.3.4.
Masakazu Kakumu, et al., "(PASPAC with Low Contact Resistance and High Reliability in CMOS LSI's", 1987 Symposium on VLSI Technology, IEEE, May 18-21, 1987, pp. 77-78.
D. Kenney, et al., "A Buried-Plate Trench Cell for a 64-Mb DRAM", 1987 Symposium on VLSI Technology,IEEE, May 18-21, 1987, pp. 14-15.
K.H. Kusters et al., "A Stacked Capacitor Cell with a Fully Self-Aligned Contact Process for High-Density Dynamic Random Access Memories", J. Electrochem. Soc.,Aug. 1992, pp. 2318-2321.
K.H. Kusters, "A High Density 4Mbit dRAM Process Using a Fully Overlapping Bitline Contact (FoBIC) Trench Cell", pp. 93-94.
E. Magdo and S.D. Malaviya, IBM Technical Disclosure Bulletin, "Self-Aligned Metal Bipolar Process", vol. 24, No. 10 Mar. 1982, pp. 5128-5131.
S. Subbanna, et al., "A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic", IEEE, 1993, pp. 17.3.1-17.3.4.
K. Ueno, et al., "A Quarter-Micron Planarized Interconnection Technology With Self-Aligned Plug", IEEE, Apr., 1992, pp. 11.6.1-11.6.4.
Stanley Wolf, PhD. et al., vol. I-, "Process Technology", Silicon Processing for the VLSI Era, 1986, pp. 453-454.
Stanley Wolf, PhD., vol. II, "Process Integration", Silicon Processing for the VLSI Era,Apr. 22, 1992, pp. 222-237.
Everhart Caridad
Intel Corporation
LandOfFree
Process for forming an integrated structure comprising a self-al does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for forming an integrated structure comprising a self-al, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming an integrated structure comprising a self-al will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1214533