Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-19
2002-12-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06495461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated-circuit device used in microprocessors, DRAMs (dynamic random access memories), theoretical circuits and so forth, and more particularly to a semiconductor device characteristic of structure at its contact holes. It also relates to a process for forming amorphous titanium silicon nitride on a substrate.
2. Related Background Art
FIG. 11
is a schematic cross-sectional view at the part of a contact hole of a conventional semiconductor integrated-circuit device.
On the surface of a substrate
1
such as a silicon wafer, an insulating film
2
is formed where the contact hole has been formed. A barrier layer
4
is formed on the surface of the insulating film
2
inclusive of that on the sidewall of the contact hole and on the substrate surface to which the bottom of the contact hole is laid bare. A conductive layer
8
such as an Al—Cu or Al—Si—Cu layer is formed on the barrier layer
4
.
The aluminum (Al) which is an element constituting the conductive layer
8
that functions as an electrode or wiring tends to react with the silicon (Si) which is an element constituting the substrate. Hence, in order to prevent such reaction, the barrier layer
4
is provided between the substrate and the conductive layer. Titanium nitride (TiN) is used in the barrier layer.
FIG. 12
shows an example of a contact hole disclosed in Japanese Patent Application Laid-Open No. 8-274173.
In this example, two layers, a titanium (Ti) layer
3
and a TiN barrier layer
4
, are formed on the insulating film
2
and the sidewall and bottom of the contact hole, and a W (tungsten) wiring
9
is formed in the contact hole. A TiN layer
5
, a Ti layer
6
and TiN layer
7
are further provided as a triple diffusion barrier for preventing the wiring
8
formed of Al—Cu or the like from reacting with the tungsten wiring
9
.
FIG. 13
shows a structure disclosed in Japanese Patent Application Laid-Open No. 8-316233. This structure is basically the same as the prior art shown in
FIG. 11
, except that an insulating film
10
of silicon nitride (SiN) is formed on the surface of the substrate
1
and an insulating film
2
having contact holes is formed thereon.
In all the prior art described above, the barrier layer
4
is so provided as to cover the whole substrate surface, i.e., the surface of insulating film
2
and the sidewall and bottom of each contact hole.
Then the barrier layer has a thickness of from 30 nm to 50 nm. Hence, if the contact hole has a side length smaller than 0.25 &mgr;m, the inside of the contact hole may come to be substantially filled up with the barrier layer
4
, resulting in a high contact resistance. For example, a barrier layer of 50 nm thickness is formed in a contact hole of 0.18 &mgr;m in side length, the inside of the contact hole is half or more held by the barrier layer.
Accordingly, it is desired to form the barrier layer comprised of TiN, only on the bottom of the contact hole, i.e., only on the surface of the substrate
1
which is laid bare at the contact hole. However, any growth process for such selective formation is unknown.
Under such circumstances, a method is available in which, using titanium silicon nitride (TiSiN) in place of TiN, a barrier layer comprised of TiSiN is formed only on the bottom of the contact hole.
FIG. 14
shows how it stands.
A titanium silicide (TiSi
2
) film
11
is formed on the surface of a substrate
1
, and an insulating film
2
having a contact hole is formed on the titanium silicide film
11
. Then a titanium silicon nitride (TiSiN)
12
is formed only on the bottom of the contact hole. No titanium silicon nitride is present on the sidewall of the contact hole.
This structure can be set up by forming the TiSi
2
film on the substrate comprised of silicon (Si), forming the insulating film thereon, making the contact hole, and then nitriding the Ti uncovered surface, laid bare to the bottom of the contact hole (H. Shinriki et al., Extended Abstracts on SSDM (1994), p.946).
However, this method has a possibility of causing impurities to be sucked up into TiSi
2
as a result of high-temperature heat treatment.
Meanwhile, as a method different from the above selective film formation on the contact hole bottom surface, Extended Abstracts of The 43rd Spring Meeting (1996), The Japan Society of Applied Physics and Related Societies, page 673, 26p-Q-4, discloses a method in which a TiSiN film is formed over the whole substrate surface at a low temperature. In this method, the TiSi
2
film is formed on the silicon substrate in a thickness of 70 nm, and the back thereof is exposed to nitrogen (N
2
) plasma. It is done at an N
2
pressure of 80 mTorr and an applied power of 300 W.
However, the TiSiN film thus obtained by N
2
plasma processing at a pressure of 80 mTorr and a temperature of 50° C. is, as will be detailed later, a coarse crystalline film in which titania (TiO
2
) is much produced, and can not be made into a uniform continuous film if it is formed in a thin film of about 10 nm. Moreover, it has been found that this coarse crystalline TiSiN film may cause a low film quality for the conductor film to be deposited thereon. Hence, the TiSiN film formed by this method is not suitable for its working according to the design criterion of a minimum working size of less than 0.25 &mgr;m.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a structure having a barrier layer with a low contact resistance.
Another object of the present invention is to provide a structure that can attain a good electrical conduction even at fine contact holes of smaller than 0.25 &mgr;m in side length.
Still another object of the present invention is to provide a structure having a barrier layer that enables formation of a conductor film of good quality on the barrier layer.
A further object of the present invention is to provide a process for forming by CVD (chemical vapor deposition) a titanium silicon nitride film that can form a good barrier layer.
The semiconductor device according to the present invention is a semiconductor device comprising a substrate, a conductor and an insulating film provided on the surface of the substrate, part of the surface of the substrate being electrically connected with the conductor through a contact hole made in the insulating film, wherein;
a barrier layer present between part of the surface of the substrate and the conductor is provided only on the bottom of the contact hole; and
the barrier layer provided on the bottom comprises amorphous titanium silicon nitride.
The process for forming amorphous titanium silicon nitride according to the present invention is a process for forming amorphous titanium silicon nitride on the surface of a substrate, comprising the steps of:
a) forming titanium silicide on the surface of the substrate; and
b) exposing the titanium silicide formed on the surface of the substrate, to nitrogen plasma while maintaining the temperature of the substrate within the range of from 200° C. to 450° C. and keeping the inside of a reaction chamber at a pressure of 13.3 Pa or above, to form the amorphous titanium silicon nitride.
The process for forming amorphous titanium silicon nitride according to the present invention is also a process for forming amorphous titanium silicon nitride on the surface of a substrate provided in a reaction chamber, comprising the step of introducing a tetradiethylaminotitanium gas and an Si
2
H
6
gas into the reaction chamber while maintaining the substrate temperature within the range of from 200° C. to 450° C. and keeping the inside of the reaction chamber at a pressure of from 13.3 Pa to 267 Pa, to form the amorphous titanium silicon nitride on the substrate.
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patent: 5091210 (1992-02-01), Mikoshiba et al.
patent: 5179042 (1993-01-01), Mikoshiba et al.
patent: 5180687 (1993-01-01), Mikoshiba et al.
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patent: 5659057 (1997-08-01), Vaartstra
pate
Masu Kazuya
Matsuhashi Hideki
Tsubouchi Kazuo
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Hoang Quoc
Nelms David
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