Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2000-01-10
2001-06-26
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C432S120000, C432S120000, C432S120000
Reexamination Certificate
active
06251738
ABSTRACT:
TECHNICAL FIELD
The present invention relates to heterojunction bipolar transistors. More particularly, this invention relates to a process for forming a silicon-germanium base of a heterojunction bipolar transistor.
BACKGROUND OF THE INVENTION
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an “on” state and an “off” state.
The bipolar transistor is an electronic device with two p-n junctions in close proximity. The bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions (the emitter-base and collector-base junctions) are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called “bipolar-transistor action.”
External leads can be attached to each of the three regions and external voltages and currents can be applied to the device using these leads. If the emitter and collector are doped n-type and the base is doped p-type, the device is an “npn” transistor. Alternatively, if the opposite doping configuration is used, the device is a “pnp” transistor. Because the mobility of minority carriers (i.e., electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors in which the emitter is formed of silicon and the base of a silicon-germanium alloy have recently been developed. The silicon-germanium alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The use of silicon-germanium for the base can enhance the efficiency of carrier injection from the emitter into the base and, in consequence, current gain “g” becomes sufficiently high even though the impurity concentration in the silicon-germanium base is made higher than that in the conventional silicon base by more than one order of magnitude. With a silicon-germanium base, high performance at high frequencies can be realized by sufficiently raising the doping level in the base and reducing the base width. Furthermore, there is a possibility of improving the cut-off frequency (shortening the emitter-base diffusion time, &tgr;
ed
) and, consequentially, further enhancing the high-frequency characteristics by grading the germanium profile in the silicon-germanium base. The advanced silicon-germanium bipolar complementary metal-oxide-semiconductor (BiCMOS) technology uses a silicon-germanium base in the heterojunction bipolar transistor. In the high frequency (such as multi-GHz ) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high speed wired and wireless communications. Silicon-germanium BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the integration of heterojunction bipolar transistors with standard CMOS, yielding the so-called “system on a chip.”
It is advantageous to have a higher germanium content in the silicon-germanium base. It has been a major challenge, however, to deposit high quality silicon-germanium film with a high germanium content. It is well known that germanium has a constant about 4% larger than the lattice constant of silicon. When silicon-germanium is grown on a silicon substrate, silicon-germanium will experience a compressive strain due to the lattice mismatch between the silicon-germanium and the silicon substrate. As the silicon-germanium thickness increases above a certain thickness, known as the critical thickness, the energy of the misfit strain increases such that it becomes energetically favorable for dislocation to generate in the alloy film. It is well known that dislocation is detrimental to device performance, especially for bipolar devices, leading to high leakage current and low breakdown. As the germanium content in the silicon-germanium increases, the critical thickness decreases due to a larger lattice mismatch. For a germanium content of 50%, the critical thickness is only about 10 nm, which is too thin for most of the heterojunction bipolar transistor base layers.
For example, silicon-germanium with 10% germanium content has a critical thickness of about 100 nm. With a 100 nm base thickness, previous research has shown that the germanium content can be increased to about 15% without severely degrading the device performance. Further increases of germanium content above 20% produce degradation of the heterojunction bipolar transistor performance due to the generation of misfit dislocations in the silicon-germanium base.
One process of fabricating a heterojunction bipolar transistor having a silicon-germanium base is provided by Fumihiko Sato et al. in their article titled, “A Self-Aligned SiGe Base Bipolar Technology Using Cold Wall UHV/CVD and Its Application to Optical Communication IC's,” IEEE Trans. Electron Devices, Vol. 42, pp. 82-88 (1995). The heterojunction bipolar transistor of Sato et al. uses selective growth of a silicon-germanium base film on a specially constructed structure to form a silicon-germanium base, a process which is very complex. In addition, the silicon-germanium base of Sato et al. is surrounded on the sides by a dielectric layer when it is formed, which affects the strain release of the silicon-germanium base.
U.S. Pat. No. 5,399,511 issued to Taka et al. provides another process of fabricating a heterojunction bipolar transistor having a silicon-germanium base. Unfortunately, the process of Taka et al. suffers from some of the same limitations as that of the process of Sato et al. Specifically, the silicon-germanium base of Taka et al. is surrounded on the sides by a dielectric layer when it is formed, which affects the strain release of the silicon-germanium base.
There remains a need for a process of forming a silicon-germanium base of a heterojunction bipolar transistor which has a high germanium content in the base and which does not generate misfit dislocations.
SUMMARY OF THE INVENTION
The deficiencies of the conventional processes used to form silicon-germanium bases in heterojunction bipolar transistors show that a need exists for a new process for forming a silicon-germanium base with a high germanium content for a heterojunction bipolar transistor. To overcome the shortcomings of conventional processes for forming silicon-germanium bases, a new process is provided. It is an object of the present invention to provide a new process for forming a silicon-germanium base for a heterojunction bipolar transistor.
In a first embodiment, a process for forming a silicon-germanium base comprises the steps of forming a silicon substrate having a mesa surrounded by a trench, depositing a silicon-germanium layer on the substrate, and removing the silicon-germanium layer adjacent the mesa to form the silicon-germanium base. In a second embodiment, a process for forming a silicon-germanium base comprises the steps of forming a silicon substrate having a mesa surrounded by a trench, forming a dielectric layer in the trench adjacent the mesa, and growing a silicon-germanium
Dang Trung
International Business Machines - Corporation
Ratner & Prestia
Schechter, Esq. Marc D.
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