Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-06-05
2001-06-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S729000, C438S730000, C438S731000, C438S798000, C427S569000
Reexamination Certificate
active
06245686
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor fabrication and more particularly to a semiconductor wafer processing apparatus including a barrier layer material that facilitates refurbishing of the apparatus.
BACKGROUND OF THE INVENTION
In the field of semiconductor fabrication, a variety of process steps results in the contamination of the apparatus or equipment used to perform a particular processing step.
FIG. 1
depicts a conventional wafer processing apparatus
100
illustrative of a high density plasma (HDP) reactor including a semiconductor plate
109
and quartz sidewalls
112
that define a chamber
106
. Apparatus
100
includes an electrostatic chuck (ESC)
102
that is suitable for receiving a semiconductor wafer
104
within chamber
106
and a set of coils
108
configured to produce an electromagnetic field within chamber
106
.
Introducing appropriate gases into chamber
106
when the coils
108
are producing an electromagnetic field while maintaining chamber
106
at an appropriate pressure will result in the formation of a plasma as is well known in the field. In one embodiment, the plasma generated in chamber
106
is used to etch material from wafer
104
, which typically includes numerous layers of differing materials. During the plasma etch of one of the materials, it is possible to expose portions of an underlying material.
When portions of an underlying material are exposed, the plasma in chamber
106
may generate atomic particles comprised of the underlying materials. During a plasma etch of an interlevel dielectric, for example, it is possible to release metallic particles (or other contaminants) from an underlying interconnect layer into chamber
106
. The presence of these metallic particles in chamber
106
during a plasma etch may result in an undesired diffusion or high energy physical implant process in which the metallic particles are incorporated into the surfaces, such as plate
109
, of apparatus
100
that are exposed to chamber
106
. In fabrication processes utilizing copper interconnects, for instance, a post-copper oxide etch process, such as a via etch, may introduce copper atoms into plate
109
and sidewalls
108
.
FIG. 2
depicts an alternative embodiment of apparatus
100
illustrating an inductively coupled, parallel plate etch system. This embodiment of apparatus
100
includes a set of coils
120
that are configured to form an electro-magnetic field in a chamber
116
that is substantially enclosed by silicon dome
110
. As depicted in
FIG. 2
, system
100
may further include quartz lights or heat lamps
122
. Apparatus
100
of
FIG. 2
is suitable for a variety of processes including the dielectric etch process described with respect to apparatus
100
of FIG.
1
. Similar to apparatus
100
of
FIG. 1
, a semiconductor process, such as a plasma oxide etch, performed in apparatus
100
of
FIG. 2
may result in the unwanted contamination of silicon dome
110
that can affect the generated plasma and result in an etch stop condition.
In some of the more common materials (e.g., silicon) typically utilized for plate
109
of FIG.
1
and dome
110
of
FIG. 2
(collectively referred to herein as enclosures), copper atoms are believed to be highly mobile. As these mobile and conductive particles are introduced into an enclosure, the electrical characteristics of the enclosure may be affected thereby altering the characteristics of the electromagnetic field produced by coils
108
and
120
in chambers
106
and
116
respectively. The alteration of the electromagnetic field by the presence of mobile contaminants in an enclosure may negatively affect the plasma characteristics and possibly result in a less efficient etch process. If the plasma is sufficiently affected by the presence of conductive particles in the enclosure, an etch stop condition may result in which the process is entirely unable to etch vias into an oxide layer of wafer
104
.
In addition, typical etch processes such as the plasma etch of silicon-oxide films utilizing a carbon fluorine chemistry tend to result in the formation of a polymer layer on the exposed surfaces of an enclosure. If the thickness of the polymer layer formed on the enclosure is sufficient, the dome may be unable to contribute silicon or other atoms that participate in the chemistry of the plasma etch process thereby further decreasing the efficiency of the process.
In the apparatus
100
of both FIG.
1
and
FIG. 2
, a contaminated plate
109
or dome
110
resulting from extended processing typically requires periodic replacement or refurbishing. Typically, the replacement of plate
109
or dome
110
is undesirably costly. In addition, conventional methods of refurbishing enclosures typically require bead blasting or other similarly crude cleaning processes necessitating the removal of the enclosure from apparatus
100
. After an enclosure is refurbished, it must be reinstalled on apparatus
100
and re-qualified. Skilled artisans appreciate that the removal and requalification of an enclosure can be a costly and time-consuming process. Therefore, it would be highly desirable to implement an apparatus and method that would minimize or eliminate overhead associated with replacing or refurbishing an enclosure such as plate
109
or dome
110
.
REFERENCES:
patent: 5158644 (1992-10-01), Cheung et al.
patent: 5556713 (1996-09-01), Leverant
patent: 5683458 (1997-11-01), Hartig et al.
patent: 6046425 (2000-04-01), Kaji et al.
patent: 6193802 (2001-02-01), Pang et al.
Babbitt Danny R.
Farber David G.
Hartig Michael J.
Koh Ai
Rivers Jason A.
Gayka Alexander G.
Motorola Inc.
Niebling John F.
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