Process for forming a metal interconnect

Details Process for forming a metal interconnect Process for forming a metal interconnect

2005-08-16

2005-08-16

Guerrero, Maria F. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S645000, C438S691000, C438S692000, C438S693000, C438S959000

Reexamination Certificate

active

06930037

ABSTRACT:
This invention relates to a process for forming a metal interconnect comprising the steps of forming a concave in an insulating film formed on a substrate, forming a barrier metal film on the insulating film, forming an interconnect metal film over the whole surface such that the concave is filled with the metal and then polishing the surface of the substrate by chemical mechanical polishing, characterized in that the polishing step comprises a first polishing step of polishing the surface such that the interconnect metal film partially remains on the surface other than the concave and a second polishing step of polishing the surface using a polishing slurry controlling a polishing-rate ratio of the interconnect metal to the barrier metal to 1 to 3 both inclusive, until the surface of the insulating film other than the concave is substantially completely exposed. According to this invention, dishing and erosion can be prevented and a reliable damascene interconnect with a small dispersion of an interconnect resistance can be formed.

REFERENCES:
patent: 4414125 (1983-11-01), Keil, deceased et al.
patent: 4892612 (1990-01-01), Huff
patent: 5516346 (1996-05-01), Cadien et al.
patent: 5854145 (1998-12-01), Chandler et al.
patent: 5959359 (1999-09-01), Tsuchiya
patent: 6063306 (2000-05-01), Kaufman et al.
patent: 6140225 (2000-10-01), Usami et al.
patent: 8-83780 (1996-03-01), None
patent: 10-44047 (1998-02-01), None
patent: 10-46140 (1998-02-01), None
patent: 10-163141 (1998-06-01), None
patent: 11-238709 (1999-08-01), None
patent: 2001-010276 (2001-11-01), None
patent: WO 00/52230 (2000-09-01), None
Yasutaka et al. (JP 08083780) (Translation).
Hayasaki et al. “A new two-step metal-CMP technique for a high performance multilevel interconnects featured by Al and “Cu in low E, organic film” metallizations”, 1996, IEEE, pp. 88-89.

Affiliated with

Also associated with

Rating

Process for forming a metal interconnect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for forming a metal interconnect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for forming a metal interconnect will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3517136