Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-05-16
2004-11-02
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S301000, C438S303000, C438S581000, C438S583000, C438S664000
Reexamination Certificate
active
06812121
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices, and more specifically to a process for forming a low resistivity titanium silicide layer at the surface of doped areas of a silicon semiconductor substrate.
2. Description of Related Art
Titanium silicide is the predominant silicide used in the integrated microelectronic device industry, in particular in VLSI and ULSI technologies. Titanium silicide TiSi
2
is a polymorphic material that can exist in a base-centered orthorhombic form, which is known as the C49 phase, or in a face-centered orthorhombic form, which is known as the C54 phase. Titanium silicide has a high resistivity of about 75 &mgr;ohm.cm in the C49 phase, and a low resistivity of about 15 &mgr;ohm.cm in the C54 phase. When a titanium film is deposited on silicon and heated, the high resistivity C49 phase is first formed at temperatures between 550° C. and 700° C., and is then transformed into the low resistivity C54 phase at temperatures above approximately 750° C. The transformation of the titanium silicide film from the C49 phase into the C54 phase is limited by a high activation energy (greater than 5.0 eV) that depends on the dopants, on the crystallinity of the silicon substrate, and on the size of the region to be silicided.
Experimentally, the high activation energy required to form the C54 phase results in a very low density of C54 nuclei being formed in a matrix of C49 phase during thermal annealing. With the current reduction in line widths (e.g., to 0.3 &mgr;m or less), it is becoming increasingly difficult to use thermal annealing to transform a structure from the high resistivity C49 phase into the low resistivity C54 phase because of a lack of C54 nuclei. As a result, the titanium silicide TiSi
2
films are either still in the form of the C49 phase or are composed of a mixture of the C49 and C54 phases. Thus, the film has a higher resistivity than would be obtained with a complete transformation to the C54 phase, and the high resistivity of the titanium silicide can decrease the performance of the semiconductor device (e.g., CMOS device) being produced.
To overcome this problem, it has been proposed to implant or deposit atoms of a refractory metal such as molybdenum or tungsten at the surface of the silicon substrate before depositing the titanium layer and forming the titanium silicide through rapid thermal annealing. It has also been proposed to use other refractory metals such as tantalum and niobium. An article entitled “Reduction of the C54-TiSi
2
phase transformation temperature using refractory metal ion implantation” by R. W. Mann et al. (Appl. Phys. Lett. 67(25), Dec. 18, 1995) discloses forming titanium silicide having a low resistivity by implanting ions of a refractory metal such as tungsten or molybdenum on a silicon substrate, depositing a thin layer of titanium, and then performing a rapid thermal treatment.
Additionally, an article entitled “TiSi
2
phase transformation characteristics on narrow devices” by Glen L. Miles et al. (Thin Solid Films 290-291 (1996), 469-472) indicates that the presence of small quantities of molybdenum during silicide formation increases the level of C54 phase precursor nuclei. The article states that the molybdenum can act as a catalyst and that there does not have to be a mixture at the interface or the creation of an amorphous silicon layer in order to improve nucleation. The use of molybdenum to promote titanium silicide transformation from the C49 phase to the C54 phase is also described in an article entitled “Salicides for 0.10 &mgr;m gate lengths: A comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization and Co processes” by Jorge A. Kittl et al. (1997 Symposium on VLSI Technology Digest of Technical Papers) and another article entitled “Novel one-step RTP Ti silicide process with low-sheet-resistance 0.06 &mgr;m gates and high drive current” by Jorge A. Kittl et al. (IEDM 97, 111 to 114).
Although doping using refractory metals such as molybdenum and tungsten improves titanium silicide transformation from the C49 phase to the C54 phase, the use of refractory metals such as molybdenum and tungsten has drawbacks. First, molybdenum and tungsten form very stable compounds with silicon, and this is detrimental to titanium silicide formation. Additionally, molybdenum or tungsten implantation is undesirable because of problems with cross-contamination of the implanted element.
Further, an article entitled “Sub-quarter micron titanium silicide technology with in-situ silicidation using high-temperature sputtering” by Kuinihiro Fujii et al. (1995 Symposium on VLSI Technology Digest of Technical Papers) discloses the pre-amorphization of the surface of a silicon substrate by arsenic implantation for the purpose of promoting titanium silicide transformation from the C49 phase to the C54 phase. However, the disclosed process gives rise to leakage at junctions, mainly in NMOS devices. Additionally, the effect on the resistivity of the titanium silicide is relatively modest.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a process for forming a low resistivity titanium silicide layer on the surface of at least one doped area of a silicon semiconductor substrate. In the process, a titanium layer is deposited on the surface of at least one doped area of the substrate, and rapid thermal annealing of the titanium-coated substrate is performed in order to form titanium silicide. Further, before performing the thermal annealing, an effective amount of a metallic element such as indium (In), gallium (Ga), tin (Sn), or lead (Pb) is implanted or deposited at the interface between the titanium layer and said at least one doped area of the silicon semiconductor substrate. Preferably, the metallic element is indium or gallium, and more preferably the metallic element is indium.
In the process of the present invention, the effective amount of the metallic element is an amount sufficient to promote titanium silicide transformation from the C49 phase to the C54 phase during the subsequent rapid thermal annealing. In preferred processes, the effective amount of the metallic element is between 1×10
13
and 5×10
14
atoms/cm
2
, more preferably between 5×10
13
and 5×10
14
atoms/cm
2
, and even more preferably between 5×10
13
and 3×10
14
atoms/cm
2
. The metallic element can be introduced at the interface between the doped area of the silicon substrate and the titanium layer through implantation of the metallic element into the doped area of the silicon substrate or through deposition on the surface of the doped area of the silicon substrate before the titanium layer is deposited. Alternatively, the metallic element may be introduced, after the titanium layer has been deposited, by diffusion or by implantation through the titanium layer. Further, the metallic element can simply be incorporated into the alloy of the target used for depositing the titanium layer by sputtering.
In preferred processes, the metallic element is implanted into the silicon substrate before the titanium layer is deposited, with the implantation depth of the metallic element being generally between 5 and 25 nm, and preferably between 8 and 20 nm. Any conventional implantation process can be used for the metallic element implantation, and preferably conventional ion beam implantation is used. The implantation energy of the metallic element is generally between 5 and 30 keV, and preferably is approximately 25 keV. In this manner, it is possible to implant a dose of 3×10
14
In/cm
2
from a solid InCl
3
target-source heated to 320° C. with a 25 keV implantation energy.
Deposition of the titanium layer can be performed by any conventional deposition process, such as physical vapor deposition (PVD). For example, it is possible to deposit a 30 nm titanium layer by PVD in approximately 15 seconds. Further, the t
Basso Marie-Thérèse
Baylac Bruno
Gerritsen Eric
Bongini Stephen
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Jorgenson Lisa K.
Nguyen Thanh
STMicroelectronics S.A.
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