Process for forming a bit-line in a MONOS device

Details Process for forming a bit-line in a MONOS device Process for forming a bit-line in a MONOS device

1999-10-25

2001-10-02

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S258000, C438S261000, C438S266000

Reexamination Certificate

active

06297143

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of the dielectric layers in semiconductor devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain.
A Flash device that utilizes the ONO structure is a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) cell. A problem exists with known MONOS cell fabrication techniques in that a thickness of a bit-line oxide layer is difficult to control which causes unpredictable MONOS cell performance. If the thickness of the bit-line oxide layer is not accurately formed, charge cannot be adequately stored within the ONO structure.
A problem occurs in that even a 5 to 10 angstrom variation in the thickness of the ONO structure's lower oxide layer can adversely affect the total amount of implanted arsenic. Thereafter, during the bit-line oxidation process, the amount of implanted arsenic affects the rate of oxidation of the bit-line oxide layer. In particular, a heavily doped arsenic implant enhances the oxidation rate. The variation of the arsenic concentration causes a twenty percent variation, or more, in the thickness of the bit-line oxidation layer. The variation in the bit-line oxidation layer produces unpredictable MONOS cell performance.
Therefore, while recent advances in MONOS cell technology have enabled memory designers to improve MONOS cells, numerous challenges exist in the fabrication of material layers within these devices. In particular, a fabrication process of MONOS cells should accommodate precise control of the thickness of a bit-line oxide layer. Accordingly, advances in MONOS cell fabrication technology are necessary to control bit-line oxide layer fabrication and insure high quality MONOS cell devices.
BRIEF SUMMARY OF THE PREFERRED EMBODIMENTS
Such needs are met or exceeded by the present method for fabricating a MONOS cell. According to an aspect of the present invention a uniform bit-line oxide layer is formed to ensure a desired thickness of the bit-line oxide layer. Therefore, a quality of the MONOS cell is improved.
More specifically, in one form, a process for fabricating a buried bit-line structure for a MONOS cell includes providing a semiconductor substrate and forming mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench formed in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a chemical-mechanical-polishing process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.


REFERENCES:
patent: 5851881 (1998-12-01), Lin et al.
patent: 6117730 (2000-09-01), Komori et al.

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