Process for fabrication of FinFETs

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C257SE29130

Reexamination Certificate

active

07470570

ABSTRACT:
A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

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Yan, Ran-Hong et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Trans. Elec. Dev., Jul. 1992, 1704-1710, vol. 39, No. 7.
Park, T. et al., “Fabrication of Body-Tied FinFETs (Omega MOSFETs) Using Bulk Si Wafers,” Symp. VLSI Tech. Dig. Tech. Pap., 2003, 135-136.

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