Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-01-21
2001-05-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S683000, C438S110000, C438S113000, C438S643000, C438S651000, C438S655000, C438S664000, C438S199000
Reexamination Certificate
active
06228766
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a fabrication technology for a semiconductor integrated circuit device and, more particularly, to a process for fabricating a semiconductor device without separation between a silicide layer and an insulating layer.
DESCRIPTION OF THE RELATED ART
The semiconductor integrated circuit device has been increased in integration density, and, accordingly, the circuit components are miniaturized. A field effect transistor has a narrow gate electrode and shallow source/drain regions, and the narrow gate electrode and the shallow source/drain regions encounter a problem in larger resistance. The large resistance retards the signal propagation, and the integrated circuit can not achieve a signal processing speed to be expected.
A salicide (self-aligned silicide) structure is proposed for reducing the resistance. Titanium is used for the salicide structure, because titanium silicide has the lowest resistivity of presently available silicides.
FIGS. 1A
to
1
H illustrate the prior art process for fabricating a MOS (metal-oxide-semiconductor) field effect transistor with the salicide structure.
The prior art process starts with preparation of a p-type silicon substrate
1
, and n-type well
2
is formed in a surface portion of the p-type silicon substrate
1
. Silicon oxide is selectively grown on the major surface of the p-type silicon substrate
1
, and forms a field oxide layer
3
. The field oxide layer
3
defines active areas
4
assigned to MOS field effect transistors and an inactive area
5
assigned to a scribe region. The active areas
4
and the inactive area
5
are thermally oxidized so as to grow thin gate oxide layers
6
and
7
, and polysilicon is deposited over the entire surface of the resultant semiconductor structure. Phosphorous is introduced into the polysilicon layer so as to reduce the resistivity.
A photo-resist etching mask (not shown) is patterned on the polysilicon layer by using photo-lithographic techniques, and the polysilicon layer is selectively removed by using a dry etching technique. Thus, the polysilicon layer is patterned into gate electrodes
8
and
9
on the thin gate oxide layers
6
/
7
. The photo-resist etching mask is stripped off.
A photo-resist ion-implantation mask
10
is patterned on the resultant semiconductor structure by using the photo-lithographic techniques, and the n-type well
2
is covered with the photo-resist ion-implantation mask
10
. Phosphorous is ion implanted into the p-type silicon substrate
1
, and lightly doped n-type regions
11
,
12
and
13
are formed in the active area
4
and the inactive area
5
. The lightly-doped n-type regions
11
and
12
are self-aligned with the gate electrode
8
. The resultant semiconductor structure is shown in FIG.
1
A. The photo-resist ion-implantation mask
10
is stripped off.
A photo-resist ion-implantation mask
14
is patterned on the resultant semiconductor structure by using the photo-lithographic techniques, and the n-type well
2
is uncovered with the photo resist ion-implantation mask
14
. The photo-resist ion-implantation mask
14
is the inversion of the photo-resist ion-implantation mask
10
, because the photo-masks (not shown) are easily designed. For this reason, the phosphorous is ion implanted into the inactive area
5
. Boron is ion implanted into the n-type well
2
, and p-type impurity regions
15
a
/
16
a
are formed in the n-type well
2
in a self-aligned manner with the gate electrode
9
as shown in FIG.
1
B. The photo-resist ion-implantation mask
14
is stripped off.
Silicon oxide or silicon nitride is deposited over the entire surface of the resultant semiconductor structure, and the silicon oxide layer or the silicon nitride layer is anisotropically etched so as to form side wall spacers
15
/
16
on both sides of the gate electrodes
8
/
9
. Silicon oxide is deposited over the entire surface of the resultant semiconductor structure, and forms a covering layer
17
.
A photo-resist ion-implantation mask
18
is patterned on the covering layer
17
, and the n-type well
2
is covered with the photo-resist ion-implantation mask
18
. Arsenic is ion implanted into the active area
4
and the inactive area
5
, and heavily-doped n-type impurity regions
19
,
20
and
21
are formed therein. The heavily-doped n-type impurity regions
19
/
20
are self-aligned with the side wall spacers
15
, and form source/drain regions
22
/
23
together with the lightly-doped n-type impurity regions
11
/
12
. The source/drain regions
22
/
23
have the LDD (lightly doped drain) structure. The photo-resist ion-implantation mask
18
is the inversion of the photo-resist ion-implantation mask
14
, and the arsenic is also ion implanted into the inactive area
5
. For this reason, the lightly-doped n-type impurity region
13
is laminated with the heavily-doped n-type impurity region
21
. The resultant semiconductor structure is shown in FIG. C. The photo-resist ion-implantation mask
18
is stripped off.
A photo-resist ion-implantation mask
22
is patterned on the covering layer
17
, and is the inversion of the photo-resist ion-implantation mask
18
. Boron is ion implanted into the n-type well, and heavily-doped p-type impurity regions
23
/
24
are formed in a self-aligned manner with the side wall spacers
16
. The heavily-doped p-type impurity regions
23
/
24
form p-type source/drain regions
25
/
26
together with the lightly doped p-type impurity regions
15
/
16
. The p-type source/drain regions
25
/
26
have the LDD structure. The photo-resist ion-implantation mask
22
is stripped off.
Arsenic is ion implanted into the surface portions of the n-type source/drain regions
22
/
23
, the surface portions of the p-type source/drain regions
25
/
26
and the surface portions of the polysilicon gate electrodes
8
/
9
so as to produce amorphous silicon layers
27
,
28
,
29
,
30
,
31
and
32
. The ion-implantation of arsenic also forms an amorphous silicon layer
33
in the heavily doped n-type impurity region
21
. The resultant semiconductor structure is shown in FIG.
1
E.
Subsequently, the covering layer
17
is removed from the resultant semiconductor structure, and titanium is deposited over the entire surface of the resultant semiconductor structure by using a sputtering. The titanium forms a titanium layer
34
, and is held in contact with the amorphous silicon layers
27
to
33
as shown in FIG.
1
F.
The resultant semiconductor structure is placed in nitrogen ambience, and is heated to 700 degrees in centigrade or less by using a rapid thermal annealing technique. Then, the titanium reacts with the amorphous silicon, and titanium silicide layers
35
,
36
,
37
,
38
,
39
,
40
and
41
are formed on the silicon/polysilicon layers
22
,
8
,
23
,
25
,
9
,
26
and
21
, respectively. The residual titanium reacts with the nitrogen, and is converted to a titanium nitride layer
42
as shown in FIG.
1
G.
The titanium nitride layer
42
is etched away in wet etchant containing aqueous ammonia and hydrogen peroxide. The titanium silicide layers
35
to
41
are left on the silicon/polysilicon layers
22
,
8
,
23
,
25
,
9
,
26
and
21
. The titanium silicide layers
35
to
41
are rapidly annealed at higher temperature than the previous rapid thermal annealing. Then, the change of phase takes place in the titanium silicide layers
35
to
41
, and the resistivity of titanium silicide is decreased.
Undoped silicon oxide is deposited over the entire surface of the resultant semiconductor structure, and forms a silicon oxide layer
43
. Borophosphosilicate glass, phosphosilicate glass or boro-phosphosilicate glass is deposited over the undoped silicon oxide layer
43
, and forms an inter-level insulating layer
44
. The inter-level insulating layer
44
is heated to about 800 degrees in centigrade for increasing the density. The undoped silicon oxide layer
43
and the inter-level insulating layer
44
as a whole constitute an inter-level insulating structure
45
as shown in FIG.
1
H.
The
Bowers Charles
Foley & Lardner
NEC Corporation
Pham Thanhha
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