Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-24
2003-04-08
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S592000, C438S685000
Reexamination Certificate
active
06544890
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a fabrication technology for a semiconductor device and, more particularly, to a process for fabricating a semiconductor device having silicide layers and a sputtering system used therein.
DESCRIPTION OF THE RELATED ART
FIG. 1
illustrates a typical example of the sputtering system. The prior art sputtering system has a load-lock chamber
401
, a transfer chamber
402
and a deposition chamber
450
, and a gate valve
404
is provided between the load-lock chamber
401
and the deposition chamber
450
. A wafer holder/conveying arm
405
is movable between the load-lock chamber
401
and the deposition chamber
450
through the gate valve
404
, and conveys a semiconductor wafer
406
between the load-lock chamber
401
and the deposition chamber
450
. Another gate valve
404
is connected between the transfer chamber
402
and the deposition chamber
450
.
Though not shown in
FIG. 1
, a target is opposed to the semiconductor wafer
406
in the deposition chamber
450
, and is subjected to ion-bombardment so as to deposit material such as metal with a high-temperature melting-point on the semiconductor wafer
406
. In the following description, the term “metal with a high-temperature melting-point”.
An air valve
407
is connected between the load-lock chamber
401
and the outside, and an inert gas inlet port
408
is open to the load-lock chamber
401
. Although a wafer inlet port is further connected to the load-lock chamber
401
, it is not shown in FIG.
1
.
The prior art sputtering system is available for a sliced process disclosed in Japanese Patent Publication of Unexamined Application (laid-open) No. 9-69497.
FIGS. 2A
to
2
D shows the prior art process disclosed in the Japanese Patent Application of Unexamined Application. The prior art process starts with preparation of a p-type silicon substrate
301
. An n-type well
302
is formed in a surface portion of the p-type silicon substrate
301
. A field oxide
303
is selectively grown on the p-type silicon substrate
301
through a selective oxidization process, and defines active regions.
Silicon oxide is selectively grown on the active regions. The active regions are covered with silicon oxide layers. Polysilicon is deposited over the entire surface of the resultant structure, and the silicon oxide layers are over-lain by the polysilicon layer. Phosphorous is doped into the polysilicon layer so as to reduce the resistivity of the polysilicon layer. A photo-resist etching mask is formed on the phosphorous-doped polysilicon layer by using a photo-lithography, and the phosphorous-doped polysilicon layer and the silicon oxide layers are selectively etched by using a dry etching technique. Then, gate oxide layers
304
and gate electrodes
305
are left on the active regions.
A photo-resist ion-implantation mask is formed on the resultant structure by using the photo-lithography. The n-type well
302
is covered with the photo-resist ion-implantation mask, and the p-type silicon substrate
301
is exposed to a hole formed in the photo-resist ion-implantation mask. N-type dopant impurity is ion implanted into the p-type silicon substrate
301
. Then, lightly-doped n-type impurity regions
306
are formed in a self-aligned manner with the gate electrode
305
. The photo-resist ion-implantation mask is stripped off.
Another photo-resist ion-implantation mask is formed on the resultant structure by using the photo-lithography. The n-type well
302
is exposed to a hole formed in the photo-resist ion-implantation mask, and the p-type silicon substrate
301
is covered with the photo-resist ion-implantation mask. P-type dopant impurity is ion implanted into the n-type well
302
. Then, lightly-doped p-type impurity regions
307
are formed in a sell-aligned manner with the gate electrode
305
. The photo-resist ion-implantation mask is stripped off.
Silicon oxide or silicon nitride is deposited over the entire surface of the resultant structure by using a chemical vapor deposition, and a silicon oxide layer or a silicon nitride layer is formed on the resultant structure. The silicon oxide layer or the silicon nitride layer is etched until the gate electrodes
305
are exposed, and side wall spacers
308
are formed on side surfaces of the gate electrodes
305
as shown in FIG.
2
A.
A photo-resist ion-implantation mask is formed on the resultant structure by using the photo-lithography. The n-type well
302
is covered with the photo-resist ion-implantation mask, and the p-type silicon substrate
301
is exposed to a hole formed in the photo-resist ion-implantation mask. N-type dopant impurity is ion implanted into the p-type silicon substrate
301
. Then, heavily-doped n-type impurity regions
309
are formed in a self-aligned manner with the side wall spacers
308
. The photo-resist ion-implantation mask is stripped off, and n-type source/drain regions
306
/
309
are formed in the p-type silicon substrate
301
.
Another photo-resist ion-implantation mask is formed on the resultant structure. The n-type well
302
is exposed to a hole formed in the photo-resist ion-implantation mask, and the p-type silicon substrate
301
is covered with the photo-resist ion-implantation mask. P-type dopant impurity is ion implanted into the n-type well
302
. Then, heavily-doped p-type impurity regions
310
are formed in a self-aligned manner with the side wall spacers
308
. The photo-resist ion-implantation mask is stripped off, and p-type source/drain regions
307
/
310
are formed in the n-type well
302
.
Subsequently, native oxide is removed from the upper surfaces of the gate electrodes
305
, the p-type silicon substrate
301
and the n-type well
302
. Cobalt is deposited over the entire surface of the resultant structure at a certain temperature between 200 degrees and 500 degrees in centigrade by using a magnetron sputtering system. The deposition temperature may be 450 degrees in centigrade. The cobalt forms a cobalt layer
311
. The cobalt layer on the gate electrode
305
, the n-type source/drain regions
306
/
309
and the p-type source/drain regions
307
/
310
reacts with the polysilicon/single crystalline silicon, and is partially converted to dicobalt monosilicide layer
312
. However, the cobalt layer
311
is left on the side wall spacers
308
and the field oxide layer
303
as shown in FIG.
2
B.
Subsequently, the resultant structure is placed in nitrogen atmosphere, and is treated with heat at 500 degrees in centigrade or higher than 500 degrees in centigrade by using a rapid thermal annealing technique. Then, the dicobalt monosilicide is converted to cobalt-monosilicide or cobalt-disilicide. As a result, the gate electrodes
305
, the heavily-doped n-type impurity regions
309
and the heavily-doped p-type impurity regions
310
are covered with cobalt-monosilicide/cobalt-disilicide layers
313
, respectively, as shown in FIG.
2
C. The residual cobalt layer
311
is partially oxidized.
Subsequently, the resultant structure is dipped into water solution containing hydrochloride acid and hydrogen peroxide. The residual cobalt layer
311
and the cobalt oxide are etched away in the water solution.
Finally, the rapid thermal annealing is carried out at 800 degrees in centigrade, and the cobalt monosilicide is converted to cobalt disilicide. As a result, the gate electrodes
305
, the heavily-doped n-type impurity regions
309
and the heavily-doped p-type impurity regions
310
are covered with cobalt disilicide layers
314
as shown in FIG.
2
D. Thus, the gate electrodes
305
, the n-type source/drain regions and the p-type source/drain regions have the cobalt disilicide layer.
The prior art sputtering system shown in
FIG. 1
is used in the deposition step for the cobalt layer
311
. The present inventor evaluated the cobalt silicide structure formed through the prior art process. The present inventor fabricated samples equivalent to the prior art semiconductor device as follows.
First, boron was ion implanted into polysilicon gate electrodes at dosage of 3&time
NEC Corporation
Trinh Michael
LandOfFree
Process for fabricating semiconductor device having silicide... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for fabricating semiconductor device having silicide..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating semiconductor device having silicide... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3001772