Process for fabricating self-aligned field emitter arrays

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156644, 156653, 156656, 156657, 156663, 156668, 313309, 313351, B44C 122, C23F 102, C03C 1500, C03C 2506

Patent

active

049649469

ABSTRACT:
A process for fabricating self-aligned field emitter arrays using a self-eling planarization technique, e.g. spin-on processes, is disclosed which includes the steps of depositing a dielectric layer on top of an array of field emitters, depositing a thin conducting film over the dielectric layer, and applying a planarization layer on the thin conducting film. Thereafter the structure is selectively etched until the underlying conducting layer is exposed in regions surrounding the field emitters, thereby defining the grid apertures. The conducting layer and dielectric layer are then selectively etched sequentially to a depth sufficient to expose a field emitter cathode tip at each field emitter site. This invention uses the concept of a self-leveling, planarizing material to define the grid apertures. After defining the aperture hole size and location, then appropriate etching processes can form the apertures themselves thereby exposing the sharp field emitters which yield an integrally gridded three-dimensional field emitter array structure.

REFERENCES:
patent: 3894332 (1975-07-01), Nathanson et al.
patent: 3981023 (1976-09-01), King et al.
patent: 3998678 (1976-12-01), Fukase et al.
patent: 4685996 (1987-08-01), Busta et al.

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