Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-29
2003-09-02
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S514000, C438S599000, C257S390000
Reexamination Certificate
active
06613661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the prevention of reverse engineering of integrated circuits (ICs), and more particularly to security techniques in which interconnections between circuit elements are made undetectable.
2. Description of the Related Art
Several techniques have been used to reverse engineer ICs. Electron (e)-beam probing with a scanning electron microscope (SEM), either through SEM photographs or voltage contrast analysis, is the standard reverse engineering mechanism, although secondary ion mass spectrometry (SIMS), spreading resistance analysis and various other techniques have also been used. A general description of e-beam probing is provided in Lee, “Engineering a Device for Electron-beam Probing”,
IEEE Design & Test of Computers,
1989, pages 36-49.
Numerous ways to frustrate unwanted attempts to reverse engineer an IC have also been developed. For example, in U.S. Pat. No. 4,766,516 to Ozdemir et al. (assigned to Hughes Aircraft Company, the assignee of the present invention), additional circuit elements that do not contribute toward the desired circuit function are added to an IC, and disguised with the visible appearance of being an ordinary part of the IC. The elements have physical modifications that are not readily visible but cause them to function in a different manner, inhibiting the proper functioning of the IC in case of an attempted copying or other unauthorized use. When the apparent function rather than the actual function of the disguised elements are copied, the resulting circuit will not operate properly.
In U.S. Pat. No. 4,583,011 to Pechar a pseudo-MOS (metal oxide semiconductor) device is given a depletion implant that is not readily visible to a copier, who would infer from the device's location in the circuit that it would be enhancement-mode. A somewhat related approach is taken in French patent publication no. 2 486 717 by Bassett et al., published Jan. 15, 1982; the circuit doping is controlled so that some devices which appear to be transistors actually function as either open or short circuits. And in U.S. Pat. No. 4,603,381 to Guttag the memory of a central processing unit is programmed by the doping of its channel regions, rather than by the presence or absence of gates, to protect permanently programmed software.
Instead of disguising circuit elements, some systems have a mechanism to protect the circuit from operating until a correct access code has been entered. Such systems are described in U.S. Pat. No. 4,139,864 to Schulman and U.S. Pat. No. 4,267,578 to Vetter.
Each of the above protection schemes requires additional processing and/or uses additional circuitry that is dedicated to security and does not contribute to the basic functioning of the circuit. This increases the cost of circuit production and complicates the circuitry.
SUMMARY OF THE INVENTION
The present invention seeks to provide a security system and method to protect against IC reverse engineering that is very difficult to detect, can be implemented without any additional fabrication steps and is compatible with computer added design (CAD) systems that allow many different kinds of logic circuits to be constructed with ease.
A logic gate is formed in a semiconductor substrate in accordance with the invention by forming doped regions in the substrate of like conductivity, and interconnecting at least some of the like conductivity regions by similarly doping interconnect portions of the substrate that run between such regions. The interconnects and the regions they connect are preferably doped simultaneously through a common dopant implantation mask to similar dopant concentrations, resulting in an integral structure for the doped regions and their interconnects. Metallized interconnects are provided as needed between p− and n− doped regions, and metallic microbridges can be used to span strips of poly-crystalline gate material that interrupt an interconnect circuit. A metallized interconnect can also be formed above the substrate to further mask a doped interconnect from observation.
Although doped implants are generally not as highly conductive as metallized interconnects, their resistance is low enough to serve an interconnect function at very large scale integration (VLSI) dimensions. Because the implanted connections are not visible to SEM or optical viewing technique, the purpose or function of the logic gates cannot be deduced, thus making the circuit very difficult to reverse engineer. Many different circuit designs that use the security technique can be stored in a CAD library and readily recalled for use as desired.
REFERENCES:
patent: 3946426 (1976-03-01), Sanders
patent: 4101344 (1978-07-01), Kooi et al.
patent: 4139864 (1979-02-01), Schulman et al.
patent: 4164461 (1979-08-01), Schilling
patent: 4267578 (1981-05-01), Vetter et al.
patent: 4291391 (1981-09-01), Chatterjee et al.
patent: 4295897 (1981-10-01), Tubbs et al.
patent: 4314268 (1982-02-01), Yoshioka et al.
patent: 4317273 (1982-03-01), Guterman et al.
patent: 4343079 (1982-08-01), Jochems
patent: 4374454 (1983-02-01), Jochems
patent: 4435895 (1984-03-01), Parillo
patent: 4471376 (1984-09-01), Morcom et al.
patent: 4581628 (1986-04-01), Miyauchi et al.
patent: 4583011 (1986-04-01), Pechar et al.
patent: 4603381 (1986-07-01), Guttag et al.
patent: 4623255 (1986-11-01), Suszko
patent: 4727493 (1988-02-01), Taylor, Sr.
patent: 4766516 (1988-08-01), Ozdemir et al.
patent: 4799096 (1989-01-01), Koeppe
patent: 4821085 (1989-04-01), Haken et al.
patent: 4830974 (1989-05-01), Chang et al.
patent: 4975756 (1990-12-01), Haken et al.
patent: 5030796 (1991-07-01), Swanson et al.
patent: 5050123 (1991-09-01), Castro
patent: 5061978 (1991-10-01), Mizutani et al.
patent: 5065208 (1991-11-01), Shah et al.
patent: 5068697 (1991-11-01), Noda et al.
patent: 5070378 (1991-12-01), Yamagata
patent: 5101121 (1992-03-01), Sourgen
patent: 5117276 (1992-05-01), Thomas et al.
patent: 5132571 (1992-07-01), McCollum et al.
patent: 5138197 (1992-08-01), Kuwana
patent: 5146117 (1992-09-01), Larson
patent: 5168340 (1992-12-01), Nishimura
patent: 5202591 (1993-04-01), Walden
patent: 5227649 (1993-07-01), Chapman
patent: 5231299 (1993-07-01), Ning et al.
patent: 5302539 (1994-04-01), Haken et al.
patent: 5308682 (1994-05-01), Morikawa
patent: 5309015 (1994-05-01), Kuwata et al.
patent: 5336624 (1994-08-01), Walden
patent: 5341013 (1994-08-01), Koyanagi
patent: 5354704 (1994-10-01), Yang et al.
patent: 5369299 (1994-11-01), Byrne
patent: 5371390 (1994-12-01), Mohsen
patent: 5376577 (1994-12-01), Roberts et al.
patent: 5384472 (1995-01-01), Yin
patent: 5399441 (1995-03-01), Bearinger et al.
patent: 5441902 (1995-08-01), Hsieh et al.
patent: 5468990 (1995-11-01), Daum
patent: 5475251 (1995-12-01), Kuo et al.
patent: 5539224 (1996-07-01), Ema
patent: 5721150 (1998-02-01), Pasch
patent: 5783846 (1998-07-01), Baukus et al.
patent: 5866933 (1999-02-01), Baukus et al.
patent: 5930663 (1999-07-01), Baukus et al.
patent: 5973375 (1999-10-01), Baukus et al.
patent: 6064110 (2000-05-01), Baukus et al.
patent: 6294816 (2001-09-01), Baukus et al.
patent: 0528 302 (1993-02-01), None
patent: 2486717 (1982-01-01), None
patent: 2486.717 (1982-01-01), None
patent: 2 059 156 (1981-04-01), None
patent: 56-101689 (1981-08-01), None
patent: 58-190064 (1983-11-01), None
patent: 59008352 (1984-01-01), None
patent: 62-130538 (1987-06-01), None
patent: 63-129647 (1988-06-01), None
patent: 2-46762 (1990-02-01), None
patent: 02237038 (1990-09-01), None
patent: 2-290043 (1990-11-01), None
patent: 05275529 (1993-10-01), None
patent: 05304207 (1993-11-01), None
patent: 63129647 (1998-06-01), None
patent: WO92/02042 (1992-02-01), None
U.S. patent application Ser. No. 07/278,889, Crafts, filed Dec. 2, 1988.
Sze, “Physics of Semiconductor Devices”, 2d Edition, John Wiley & Sons, 1981, pp. 433.
Patent Abstracts of Japan vol. 016, No. 197 (p-1350) May 12, 1992 & JP-A-40 28 092 (Toshiba Corp), abstract.
Lee, “Engineering a Device for Electron-beam Probing”,IEEE Design and Test of Computers,
Baukus James P.
Chow Lap-Wai
Clark Jr. William M.
Kramer Allan R.
Chaudhuri Olik
Duraiswamy V. D.
Hughes Electronics Corporation
Kebede Brook
Sales M. W.
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