Process for fabricating narrow polycrystalline silicon members

Details Process for fabricating narrow polycrystalline silicon members Process for fabricating narrow polycrystalline silicon members

1975-10-29

1977-05-31

Van Horn, Charles E.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29580, 148187, 156657, 156662, H01L 21312

Patent

active

040267407

ABSTRACT:
A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.

REFERENCES:
patent: 3460007 (1969-08-01), Scott
patent: 3600651 (1971-08-01), Duncan
patent: 3721593 (1973-03-01), Hays et al.
patent: 3750268 (1973-08-01), Wang
patent: 3817794 (1974-06-01), Beadle et al.
patent: 3829335 (1974-08-01), Allison et al.
patent: 3940288 (1976-02-01), Tagagi et al.

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