Process for fabricating lightly doped drain MOS devices

Details Process for fabricating lightly doped drain MOS devices Process for fabricating lightly doped drain MOS devices

1986-10-23

1988-05-17

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156653, 156657, 156656, 1566591, 156662, 437 29, 437 34, 437 41, 437154, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

047448598

ABSTRACT:
A process is disclosed for fabricating a lightly doped drain field effect transistor structure. The process includes the steps of forming a first layer of insulating material 25 on a P type substrate 10. A gate electrode which includes a polysilicon portion 28 and a metal silicide portion 30 is formed on the gate oxide 25. An etch resistant layer 36 is deposited across the structure, typically on an underlying layer of silicon dioxide 27, to protect the structure from subsequent reactive ion etching. On the etch resistant layer 36, an etchable layer of material 42 is deposited and defined into spacer regions 44. The spacer regions 44, in conjunction with the gate electrode 32, define a mask for the implantation of source and drain regions. The lightly doped portions of the source and drain regions are then formed by introducing a second impurity of different diffusivity, and allowing the higher diffusivity impurity to diffuse out from the source/drain regions 48, or by removing the spacer regions 44 before a second implant to form the lightly doped regions 54.

REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 4512073 (1985-04-01), Hsu
patent: 4577392 (1986-03-01), Peterson
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4616399 (1986-10-01), Ooka
patent: 4642878 (1987-02-01), Maeda
patent: 4658496 (1987-04-01), Beinvogl et al.

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