Process for fabricating double recess pseudomorphic high...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

Reexamination Certificate

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C438S167000, C438S180000, C438S576000

Reexamination Certificate

active

06242293

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for fabricating a double recess pseudomorphic high electron mobility transistor (PHEMT). The present application is related to U.S. Patent Application (TWC 17357), to Danzilio, the disclosure of which is incorporated by reference.
BACKGROUND OF THE INVENTION
The use of hyper-abrupt heterojunctions, on the order of as few as one atomic diameter, has enabled advanced heterostructure devices to be realized. One of the more advantageous structures is the high electron mobility transistor(HEMT) structure. A particular class of these devices is the Pseudomorphic HEMT, or PHEMT device. These are higher performance devices than their counterpart the MESFET. The PHEMT structure has higher gain than the MESFET, and this results in power devices with higher efficiency and thereby higher power capabilities which has particular ramifications in the cellular phone business which is ever seeking lower DC voltage levels for operation. Another desirable attribute of PHEMTs is a relatively fast on/off cycle. In the “on” state, due to the high conductivity of the channel, there is low signal loss through the device. In the “off” state, the combination of lower pinch-off voltage and higher breakdown voltage translates to more truly “off” behavior with reduced signal leakage between terminals. The transition from on to off of the PHEMT is relatively quick, particularly when compared to the MESFET counterpart. The basic Pseudomorphic HEMT structure uses a high purity/high mobility InGaAs material that is not intentionally doped for carrier transport. Doping introduces scattering centers, which reduce carrier mobility and velocity as is well known to one of ordinary skill in the art. At equilibrium, the heterojunction between the wide band gap material and the narrow band gap (undoped/high mobility) material creates a quantum well in the narrow bandgap semiconductor material. Electrons from the high band gap material tunnel through the energy barrier in the higher bandgap material into the quantum well. This charge transfer forms a sheet of electrons, known commonly as a two dimensional electron gas (2DEG). These 2DEG electrons in the undoped narrow band gap material possesses a very high mobility and velocity.
Conventional HEMTs rely on the hyperabrupt heterojunction between AlGaAs and GaAs. As stated, such a structure lends itself quite well to the fabrication of high electron mobility transistors which make use of the 2DEG electrons in the GaAs channel. Another material which has come into prominence in 2DEG devices is InGaAs. The heterojunction between InGaAs and AlGaAs also forms the two dimensional electron gas by virtue of the quantum well formed between the narrow band gap InGaAs and the wide band gap AlGaAs. InGaAs is also a material which, when undoped, has a very high electron mobility. The electron mobility and peak electron velocity of InGaAs is in fact much higher than GaAs. Due to differences in lattice constants of the two materials, epitaxial growth of thin InGaAs layers on GaAs substrates results in considerable strain in the InGaAs layer. This strain further deepens the quantum well formed increasing the number of electrons in the 2DEG of the Pseudomorphic HEMT, as is well known to one of ordinary skill in the art. Lattice mismatch between GaAs and InGaAs increases with Indium concentration and hence deepens the quantum well. Lattice mismatch is desirable to a degree, however if indium is introduced in too high a concentration, InGaAs lattice relaxation can occur. The lattice relaxation is the state when accumulated strain is too great and is relieved through the formation of lattice defects which behave as scattering centers. These scattering centers have a deleterious effect on carrier mobility. It has been found that molar fractions of indium to gallium of 53 to 47 are desirable. That is, In
0.53
Ga
0.47
As results in the material with a very high peak electron velocity, a relatively deep quantum well with more carriers disposed therein. However, due to severe lattice mismatch, an epitaxial structure containing In
0.53
Ga
0.47
As can only be grown on an indium phosphide substrate and device fabrication of InP based materials is relatively immature compared to GaAs. The mole fraction of indium is preferably 15-25% when InGaAs is grown on a GaAs substrate; beyond this lattice relaxation can occur and thereby reducing carrier mobility and velocity.
The desirable performance advantages of the PHEMT structure by virtue of the high mobility of the carriers of the two dimensional electron gas which is disposed in the InGaAs epitaxial layer results in a higher electron saturation velocity compared to conventional MESFET structures. Because the high mobility two dimensional electron gas is disposed deep in the epitaxial layer structure, relatively complicated techniques have to be employed in order to be able to modulate the 2DEG layer with a gate. A conventional PHEMT structure is as shown in FIG.
1
. The structure shown in
FIG. 1
has a gate
101
a source
102
and a drain
103
. The n
+
GaAs layer
104
is highly doped to effect the Ohmic contact at the drain and source. The AlGaAs layer
105
and the InGaAs layer
106
form the required heterojunction to form the PHEMT structure. The substrate is shown at
108
, and the 2DEG conduction layer is shown at
107
. The gate recess etch is a very important step in the fabrication of all GaAs base field effect transistors. This step determines all the critical DC parameters of the device, whether the device is a PHEMT or a MESFET.
Conventional techniques for fabricating the recess require an iterative etching process. As can be readily appreciated, it is necessary to reduce the distance between the gate and the 2DEG layer to an optimum point in order to effectively modulate the 2DEG layer in operation by way of the depletion layer formed under the gate. As stated above, a double recess structure is often utilized in the PHEMT. An iterative fabrication process requires etching down through the GaAs and AlGaAs layers while sampling the current periodically. As the etching process proceeds, carriers are removed as selective regions of each layer are removed. As can be seen in
FIG. 2
, the monitoring of the current versus the depth of the etch, a large decrease in saturation current per unit of depth occurs in the first region at
201
which is n+GaAs. The region at
202
shows a reduction in the slope of the saturation current relative to the depth, as the number of carriers in the lower doped AlGaAs layer is etched. Finally, the optimal point of etch depth is shown at
203
. Beyond this point, a large number of carriers would be removed from the 2DEG layer and is shown on
FIG. 2
at
204
. Accordingly, it is necessary to etch down far enough to be able to effectively modulate the 2DEG layer but not too far as the benefits of the layer are reduced as the etched surface becomes too close. Accordingly, the optimal point is at the knee of the curve shown at
203
. As stated, the double etch is required in order to increase the breakdown voltage of the PHEMT. Standard photolithographic techniques are used to effect both the first etch recess and the second etch recess. Further details of the iterative etching process done conventionally can be found in
Effects of Material Variations on the Gate Recess Behavior of Pseudomorphic HEMTS,
by Danzilio et al. 1994
U.S. Conference on GaAs Manufacturing Technology Digest of Papers p
53 the disclosure of which is specifically incorporated herein by reference.
Another important consideration is the effect of material variations. As stated in the reference to Danzilio, et al., variations of the vendor molecular beam epitaxy (MBE) can result in inconsistent epitaxial growth which appreciatively alters the characteristics of the PHEMT. Accordingly, while the etch depth for one wafer might be a certain value, this is not necessarily the appropriate depth in another wafer. Accordingly, rather than being at the proper point

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