Process for fabricating an integrated circuit package with...

Details Process for fabricating an integrated circuit package with... Process for fabricating an integrated circuit package with...

2004-11-16

2008-05-13

Pham, Thanhha S. (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S113000, C438S124000, C257SE21499, C257SE21502

Reexamination Certificate

active

07371610

ABSTRACT:
A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding material in a mold, the semiconductor die and the contacts are molded in the molding material, between the metal carrier and a metal strip. The metal carrier and the metal strip are etched away and the integrated circuit package is singulated.

REFERENCES:
patent: 4698662 (1987-10-01), Young et al.
patent: 5172213 (1992-12-01), Zimmerman
patent: 5297333 (1994-03-01), Kusaka
patent: 5311060 (1994-05-01), Rostoker et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5339216 (1994-08-01), Lin et al.
patent: 5435732 (1995-07-01), Angulas et al.
patent: 5444025 (1995-08-01), Sono et al.
patent: 5493153 (1996-02-01), Arikawa et al.
patent: 5521435 (1996-05-01), Mizukoshi
patent: 5609889 (1997-03-01), Weber
patent: 5610442 (1997-03-01), Schneider et al.
patent: 5639694 (1997-06-01), Diffenderfer et al.
patent: 5650663 (1997-07-01), Parthasarathi
patent: 5672548 (1997-09-01), Culnane et al.
patent: 5679978 (1997-10-01), Kawahara et al.
patent: 5705851 (1998-01-01), Mostafazadeh et al.
patent: 5736785 (1998-04-01), Chiang et al.
patent: 5773362 (1998-06-01), Tonti et al.
patent: 5877552 (1999-03-01), Chiang
patent: 5898219 (1999-04-01), Barrow
patent: 5901043 (1999-05-01), Lin et al.
patent: 5903050 (1999-05-01), Thurairajaratnam
patent: 5909057 (1999-06-01), McCormick et al.
patent: 5959353 (1999-09-01), Tomita
patent: 5977626 (1999-11-01), Wang et al.
patent: 5981310 (1999-11-01), DiGiacomo et al.
patent: 5985695 (1999-11-01), Freyman et al.
patent: 5986885 (1999-11-01), Wyland
patent: 6016013 (2000-01-01), Baba
patent: 6020637 (2000-02-01), Karnezos
patent: 6037658 (2000-03-01), Brodsky et al.
patent: 6051888 (2000-04-01), Dahl
patent: 6104093 (2000-08-01), Caletka et al.
patent: 6122171 (2000-09-01), Akram et al.
patent: 6175161 (2001-01-01), Goetz et al.
patent: 6181569 (2001-01-01), Chakravorty
patent: 6236568 (2001-05-01), Lai et al.
patent: 6251706 (2001-06-01), Paniccia
patent: 6313521 (2001-11-01), Baba
patent: 6323066 (2001-11-01), Lai et al.
patent: 6349032 (2002-02-01), Chan et al.
patent: 6388335 (2002-05-01), Lam
patent: 6414385 (2002-07-01), Huang et al.
patent: 6441499 (2002-08-01), Nagarajan et al.
patent: 6462405 (2002-10-01), Lai et al.
patent: 6469381 (2002-10-01), Houle et al.
patent: 6507104 (2003-01-01), Ho et al.
patent: 6525421 (2003-02-01), Chia et al.
patent: 6631078 (2003-10-01), Alcoe et al.
patent: 6656770 (2003-12-01), Atwood et al.
patent: 6734552 (2004-05-01), Combs
patent: 6800948 (2004-10-01), Martin et al.
patent: 6821821 (2004-11-01), Fjelstad
patent: 6849940 (2005-02-01), Chan et al.
patent: 2001/0015492 (2001-08-01), Akram et al.
patent: 2002/0005578 (2002-01-01), Kodoma et al.
patent: 2002/0006718 (2002-01-01), Distefano
patent: 2002/0180035 (2002-12-01), Huang et al.
patent: 2002/0185734 (2002-12-01), Zhao et al.
patent: 2003/0034569 (2003-02-01), Caletka et al.
patent: 2003/0075812 (2003-04-01), Cheng et al.
patent: 2003/0160309 (2003-08-01), Punzalan et al.
patent: 2003/0189245 (2003-10-01), Fang
patent: 2003/0226253 (2003-12-01), Mayer
patent: 100 15 962 (2001-10-01), None
patent: 02-278783 (1990-11-01), None
patent: 09-232690 (1997-09-01), None
U.S. Appl. No. 10/647,696, Mohan Kirloskar et al., “Improved Ball Grida Array Package and Process for Manufacturing Same” filed Aug. 25, 2003.
U.S. Appl. No. 10/643,961, Chun Ho Fan et al., “Improved Ball Grid Array Package and Process for Manufacturing Same” filed Aug. 20, 2003.
U.S. Appl. No. 10/372,421, Joseph Andrew Martin et al., “Improved Ball Grid Array Package” filed Feb. 24, 2003.
U.S. Appl. No. 10/323,657, Chun Ho Fan et al., “Process for Manufacturing Ball Grid Array Package” filed Dec. 20, 2002.

Affiliated with

Also associated with

Rating

Process for fabricating an integrated circuit package with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for fabricating an integrated circuit package with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating an integrated circuit package with... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3983300