Process for fabricating a self-aligned contact

Details Process for fabricating a self-aligned contact Process for fabricating a self-aligned contact

1996-11-19

2000-06-20

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438211, 438216, 438586, 438587, 438592, H01L 218238, H01L 213205, H01L 214763

Patent

active

06077763&

ABSTRACT:
A process of fabricating self-aligned contacts for a semiconductor memory IC device. The substrate of the memory device has formed thereon gate structures of the memory cell units for the memory device. The gate structures are regularly spaced apart by first sidewall spacers formed on sidewalls of the gate structures. Source/drain regions of the memory cell units are formed in the device substrate in regions between consecutive gate structures. The process includes first forming an insulating layer over the surface of the substrate, followed by anisotropically etching back the insulating layer until a predetermined thickness over and normal to the top surface of the gate structure is obtained. A photoresist layer is formed over the surface of the insulating layer, with openings exposing contact regions for the memory cell units. Second sidewall spacers are then formed on the sidewalls of the gate structures and the source/drain regions are exposed, by etching into the insulating layer through the openings. The second sidewall spacers cover the first sidewall spacers. Contacts are then formed for the memory cell units, in direct electrical contact with the source/drain regions.

REFERENCES:
patent: 5707901 (1998-01-01), Cho et al.
patent: 5783471 (1998-07-01), Chu et al.
patent: 5792687 (1998-08-01), Jeng et al.
patent: 5821573 (1998-10-01), Schunke et al.

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