Process for fabricating a non-volatile memory device

Details Process for fabricating a non-volatile memory device Process for fabricating a non-volatile memory device

2001-03-02

2003-03-04

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S439000, C438S449000, C438S450000, C438S262000

Reexamination Certificate

active

06528390

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a process for fabricating semiconductor devices containing ONO layers.
BACKGROUND
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory designers have taken advantage of the ability of silicon nitride to store charge in localized regions and have designed memory circuits that utilize two regions of stored charge within an ONO (silicon oxide/silicon nitride/silicon oxide) layer. This type of non-volatile memory device is utilized for a two-bit EEPROM. Although an ONO layer has particular advantages in a non-volatile memory device, it may be useful in many other semiconductor devices.
While the recent advances in ONO technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating a bit-line oxide layer of consistent thickness between and across memory chips presents several challenges. Typically, in the fabrication of a memory cell, an ONO layer is formed having a first silicon dioxide layer overlying the semiconductor substrate, a silicon nitride layer overlying the first silicon dioxide layer; and a second silicon dioxide layer overlying the silicon nitride layer. A layer of photoresist is then spun on to the ONO layer. A photoresist is a light sensitive film that has four basic ingredients: polymers, solvents, sensitizers, and additives. The photoresist is patterned and the semiconductor substrate is doped through the opening in the pattern. The ONO layer is then patterned by etching, using the same pattern. Next, the photoresist mask is stripped and cleaned from the ONO layer and a bit-line oxide region is thermally grown onto the semiconductor substrate in the region where the ONO layer was etched.
There are several problems that occur with the above-described conventional method for fabricating a memory cell. One problem is that the ONO etch does not have good selectivity for silicon dioxide and can damage the semiconductor substrate. A second problem is that the ONO etch occurs at a rapid rate and it is difficult to estimate when the etching process should be terminated. If the ONO etch is carried out slightly longer than necessary, the semiconductor substrate could be damaged. The low selectivity to oxide and the rapid rate of the ONO etch process necessitates early termination of the ONO etching process. As a result, a layer of residual oxide overlying the semiconductor substrate remains after the ONO etch. The residual oxide layer has an inconsistent thickness. Thus the thickness of the resulting bit-line oxide region is also not consistent, due to the residual oxide layer. This inconsistent oxide region may result in inconsistent device properties.
BRIEF SUMMARY
In one aspect, the invention is a method of fabricating a semiconductor structure which includes forming an ONO layer, a hard mask layer, and a photoresist pattern on a semiconductor substrate in this order, patterning said hard mask layer and said ONO layer through etching so as to expose the surface of said semiconductor substrate, oxidizing the exposed surface of said semiconductor substrate by using said hard mask layer as an anti-oxidation mask, and thereby forming an oxide layer selectively on said exposed surface, implanting dopants into said semiconductor substrate through said oxide layer by using said hard mask layer as an anti-implantation mask, and thereby forming bit-line regions in said semiconductor substrate, and oxidizing the surface of said semiconductor substrate through said oxide layer by using said hard-mask layer as an anti-oxidation mask, and thereby forming a bit-line oxide layer on the surface of said semiconductor substrate.
In another aspect, the invention is a method of fabricating a semiconductor structure which includes forming a masking pattern on an ONO layer, wherein the ONO layer is on a semiconductor substrate; etching the ONO layer with the masking pattern as an etching mask forming exposed regions of semiconductor substrate; epitaxially re-growing stable oxide on said exposed regions of semiconductor substrate forming a bit-line region; forming pocket regions in the substrate with a hard mask as a doping mask; forming a bit-line oxide layer on the bit-line region; and removing the hard mask.
In yet another aspect, the invention is a semiconductor device which includes a semiconductor substrate, at least one patterned ONO layer on said substrate, and at least one bit-line oxide layer on said substrate. At least 99 percent of the bit-line oxide layer has a thickness that is at least 80 percent of the thickness of the thickest part of the bit-line oxide layer.
In still another aspect, the invention is a set of semiconductor devices that include a plurality of semiconductor substrates, a plurality of patterned ONO layers, on said substrates, and a plurality of bit-line oxide layers on said substrates. At least 99 percent of the bit-line oxide layers have a thickness that is at least 80 percent of the thickness of the thickest bit-line oxide layer.


REFERENCES:
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patent: 6287917 (2001-09-01), Park et al.
patent: 6348711 (2002-02-01), Eitan
patent: 6358761 (2002-03-01), Yoo et al.
patent: 6362052 (2002-03-01), Rangarajan et al.
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patent: 6387754 (2002-05-01), Dalton et al.

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