Process for fabricating a non-silicided region in an integrated

Details Process for fabricating a non-silicided region in an integrated Process for fabricating a non-silicided region in an integrated

1994-10-03

1996-12-31

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 51, 437 54, 437200, 1566431, H01L 2170, H01L 2700, H01L 21465, H01L 21306

Patent

active

055894232

ABSTRACT:
A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).

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