Process for fabricating a multilevel interconnect

Details Process for fabricating a multilevel interconnect Process for fabricating a multilevel interconnect

1996-11-14

2000-06-20

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438628, 438629, 438634, 438644, 438674, 438675, 438677, 438680, H01L 214763

Patent

active

060777680

ABSTRACT:
A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

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