Process for fabricating a gate-drain overlapped semiconductor

Details Process for fabricating a gate-drain overlapped semiconductor Process for fabricating a gate-drain overlapped semiconductor

1991-05-30

1993-10-26

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437233, H01L 21336

Patent

active

052565858

ABSTRACT:
Disclosed is a method for fabricating a MOS transistor of the GOLD structure that allows self-aligning contact process and more precise control of low-concentration diffusion regions. The method characteristically includes the steps of: forming an oxide layer(55) over the conductive electrode(53a,54a,58a), the thickness of the oxide layer being sufficiently greater than the gate oxide layer, and depositing an insulating interlayer(61) over the semiconductor substrate after forming source and drain regions, the insulating interlayer being directionally etched through a photoresist pattern, so as to form a contact hole having a width extended up to a partial portion of the conductive electrode. The effective channel widths of the low-concentration diffusion regions may be precisely controlled only by adjusting the thickness of polysilicon (or refractory metal or silicide thereof) layer selectively deposited on the side walls of the conductive electrode.

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