Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-03
2002-04-16
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S285000, C257S286000, C257S287000, C257S327000, C257S335000, C257S344000, C257S345000, C438S289000, C438S290000, C438S291000
Reexamination Certificate
active
06373102
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor device, and more particularly to a method for fabricating a channel region of a transistor device utilizing ion implantation and the transistor device formed therefrom.
2. Description of the Related Art
FIG. 1
schematically illustrates a conventional MOS transistor; in particular, an anti-punchthrough region is formed by ion implantation with a large angle.
As shown in
FIG. 1
, the transistor is formed on a P-type silicon substrate
10
. A source region S and a drain region D are included in the silicon substrate
10
. Upon the surface of the silicon substrate
10
are sequentially formed a gate oxide layer
16
and a gate G. Insulating spacers
12
are formed on the side-walls of the gate G. Further, p-type anti-punchthrough regions
14
are formed by ion implantation with a large angle to reduce the short channel effect and punchthrough phenomenon.
However, there are many disadvantages of forming the anti-punchthrough regions
14
by ion implantation with a large angle. First, the profile of the anti-punchthrough regions
14
is dispersed and incompact in practical processes. Second, the junction capacitance between the anti-punchthrough regions
14
, the source region S and the drain region D is increased. Third, the junction leakage between the anti-punchthrough regions
14
, the source region S and the drain region D is also increased. The disadvantages described above will affect the working conditions of the transistor device.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method for fabricating a transistor device with a specific channel region so that the threshold voltage of the device is controlled better. In order to reduce the short channel effect and the punchthrough phenomenon, an anti-punchthrough region is formed by ion implantation with a predetermined angle. Furthermore, ions are implanted into a substrate in a single step. Implanting ions into a substrate in a single step can reduce masking and photolithography processes, thereby saving costs. The profile of the anti-punchthrough region is non-uniform, which is different from the prior technology, i.e., the dispersed and incompact profile.
Another object of the present invention is to provide a transistor device with a specific channel region. The specific channel region is formed by implanting ions into a substrate in a single step so that the profile of the specific channel region is compact and non-uniform. Further, the ion concentration between the channel region and the source or the drain region is lower so that the parasitic capacitance and the junction leakage are lower than that of the prior art. Accordingly, the performance of the device is improved.
To attain the first object of the present invention, an on implantation with a large angle is provided to form a transistor device with a specific channel region. The formation of the device comprises the following steps. First, a semiconductor substrate is provided, then a gate is formed on the semiconductor substrate. Subsequently, ions are implanted into the semiconductor substrate below the gate with a large angle in a single step to form a channel region with a non-uniform profile. The channel region is used to reduce the punchthrough phenomenon of the device. This results in the channel region better controlling the threshold voltage. Then, source and drain regions of the device are formed in the substrate adjacent to the channel regions.
To attain the second object of the present invention, a transistor device with a specific channel region is provided, wherein ions implanted into a substrate with a large angle form the specific channel region. The structure of the device comprises: a semiconductor substrate upon which a gate is formed; a channel region with non-uniform profile formed by ion implantation with a large angle in a single step to reduce the punchthrough phenomenon and control the threshold voltage; and a source region and a drain region arranged in the substrate below the gate.
REFERENCES:
patent: 5557129 (1996-09-01), Oda et al.
patent: 6031268 (2000-11-01), Hiroki et al.
patent: 6147383 (2000-11-01), Kuroda
patent: 6153910 (2000-11-01), Oda et al.
patent: 6177705 (2001-01-01), Tyagi et al.
Beyer Weaver & Thomas LLP
Lee Eddie
Ortiz Edgardo
Winbond Electronics Corp.
LandOfFree
Process for fabricating a channel region of a transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for fabricating a channel region of a transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating a channel region of a transistor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2928091