Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-20
2002-04-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S015000
Reexamination Certificate
active
06370674
ABSTRACT:
FIELD OF THE INVENTION
The field of the invention is that of the performance analysis of electric circuits. The components of performance analysis considered within the scope of the invention are, in particular, the determination of the speed at which a circuit or circuit component can generate output signals from input signals and the noise immunity of the circuit.
BACKGROUND OF THE INVENTION
A digital data processing circuit is normally constituted by flip-flops which store a stable state of signals, and by logic gates which connect these flip-flops by means of electric leads in order to perform logical combinations of these signals. Clock edges trigger the sending of these signals as output signals from some flip-flops and their reception as input signals by other flip-flops. After the sending of output signals from flip-flops at one clock leading edge, it is necessary for the inputs of the other flip-flops downstream to be switched to a stable state before the next clock edge. The switching instant in the input of another flip-flop depends on the speed at which the signals are propagated through the logic gates and through the leads that connect them to one another and to the flip-flops. This speed, and hence the switching instant, depends on the switching time specific to each gate and on the impedance properties of the leads: resistance, inductance and capacitance. Knowing the latest switching instant after a clock edge makes it possible to determine the shortest clock period allowable by the circuit. If the clock period is compulsory and the duration that separates a clock edge from the switching instant in the input of a flip-flop is longer than one clock period, it is necessary to change the structure of the circuit so as to reduce this duration to less than the clock period.
Even if the signals travel and combine quickly from one flip-flop memory to another, it is important for the values obtained to be as accurate as possible. One substantial source of error is the noise sensitivity of the components of the circuit. It is advantageous to evaluate the noise sensitivity of the circuit so that it can be redimensioned, if necessary, in order to increase its immunity to noise or simply ensure this immunity. The immunity of a circuit component is defined as being a change in an input voltage from a stable state that does not cause any change in the output voltage of this component. The immunity is directly related to the physical dimensions of the component. The noise level is generally obtained by multiplying the voltage difference between two stable states by the ratio of a crosstalk capacity to a total capacity of the input lead of this component.
The resistance, inductance and capacitance values of the components of a circuit are obtained from a connection list (or netlist) derived from the topological elements contained in the masks used to produce the circuit. For example, the resistance of a lead is directly proportional to its length and inversely proportional to its cross-section. The inductance of a lead is generally negligible in an integrated circuit. The capacitive effects require special precautions because for each lead, they depend on the surface area of this lead relative to the surface areas of other leads, on the distances that separate these surface areas and on the changes of the electrical loads in these other leads. In combination with the resistance of the lead, the capacitive effects constitute a determining factor in the time constant of this lead.
In order to determine this time constant in a simple way, it is common to reduce the effect of all the capacities between leads to that of a single capacity between the lead in question and a lead with a fixed potential, i.e., a lead that is not subject to any load change.
Recently, integrated circuits were produced by superposing conductive, semiconductive and insulating layers of sufficiently small thickness that the capacitive effects in a given lead of the circuit subject to load changes were essentially those caused by the capacities between the lead in question and the leads of fixed potential, constituted by the ground and the lead or leads for supplying power to the circuit. Therefore, it was sufficient to add these parallel capacities in question in order to reduce them to an equivalent capacity relative to the substrate of the circuit. The value of this capacity could be refined purely and simply by adding to it the coupling capacities with the other leads. In any case, these other signal-carrying leads of variable potential had coupling capacities that represented negligible quantities. An approximation was satisfactory.
The knowledge of this capacity relative to a fixed potential and of the resistance of the lead made it easy to determine a time constant as a function of the product of the capacity by the resistance, in each lead in question. It was then easy to deduce from this the switching instant or instant of the signals carried by this lead.
The current state of the art of using multilayered deposits to produce integrated circuits makes it possible to increase the thickness of the conductive layers in a direction perpendicular to the surface of the circuit, and to correspondingly reduce the thickness of the leads in the plane of the surface of the circuit, without reducing the cross-section of these leads, and hence without increasing the electrical resistance, or possibly even decreasing it. This makes it possible to considerably increase the level of integration of components per unit of area. On the other hand, the increase in the thickness of the insulating layers considerably reduces the coupling capacity between each lead in question and the leads of fixed potential. The effect of the coupling capacities between leads of variable potential no longer represents a negligible quantity relative to that of the coupling capacities with the leads of fixed potential, but on the contrary a predominant quantity. The approximation described in the paragraph above is no longer satisfactory.
Crosstalk is the physical phenomenon which, in a given electrical lead, causes a load change linked to a load change in another lead having a coupling capacity with the lead in question and which, reciprocally, causes in said other lead a load change linked to a load change in the lead in question. The known approximations of the prior art could lead to an overestimation or an underestimation of the time constants specific to each lead. An overestimation rung the risk of producing a conclusion that a functional circuit is not functioning. An underestimation runs the risk of not detecting a circuit's inability to function. It is possible to consider determining the time constants for each lead by mathematically solving the physical equations that govern the crosstalk phenomenon. This solution has proven to be prohibitive for a circuit comprising a large number of leads, since even though they are countable, the number of signal changes possible in a very high scale integrated circuit is nearly infinite. The determination of the switching instants, which is necessary to ensure that they remain within a clock cycle, therefore poses a problem. Moreover, crosstalk generates noise through the load changes it causes in a given lead, linked to load changes in other leads. An additional problem is posed by the need to evaluate the consequences of the crosstalk on the noise immunity of the circuit.
SUMMARY OF THE INVENTION
In order to mitigate the above-mentioned problems, the subject of the invention is a process for evaluating the performance of very high scale integrated circuits, characterized in that it comprises:
a first step in which, for each lead of said circuit, an equivalent coupling capacity value relative to a ground of fixed potential is generated as being a sum of the existing real coupling capacity values of other leads of said circuit with said lead, each of which is assigned a weighting coefficient;
a second step following said first step, in which a switching time interval in each lead is
Bull S.A.
Kondracki Edward J.
Miles & Stockbridge P.C.
Thompson A. M.
LandOfFree
Process for evaluating the performance of very high scale... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for evaluating the performance of very high scale..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for evaluating the performance of very high scale... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2882826