Process for etching vias in organosilicate glass materials...

Details Process for etching vias in organosilicate glass materials... Process for etching vias in organosilicate glass materials...

2000-10-13

2004-12-07

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000, C438S723000, C438S720000, C438S725000

Reexamination Certificate

active

06828250

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor or integrated circuit manufacture. More particularly, the present invention relates the etching of features in integrated circuits. Still more particularly, the present invention relates to the manufacture of semiconductor devices including at least one layer of organosilicate glass dielectric have a feature formed therein by etching through the dielectric.
BACKGROUND OF THE INVENTION
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO
2
, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, K, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO
2
, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO
2
may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO
2
, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-K materials”, have been developed. Many of these new dielectrics are organic compounds.
One interesting class of organic low-K materials are compounds including organosilicate glass. By way of example, but not limitation such organosilicate dielectrics include CORAL™ from Novellus Systems, Inc. of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; and Sumika Film® available from Sumitomo Chemical America, Inc., Santa Clara, Calif.
During semiconductor wafer processing, features of the semiconductor device have been defined in the wafer using well-known patterning and etching processes. In these processes a photo resist material may be deposited on the wafer and may then be exposed to light filtered by a reticle. The reticle may be a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
The development of an effective etching process for an organosilicate glass low-K film such as CORAL™ should take into account several criteria including etch rate, profile control, selectivity to underlying materials as well as critical dimension (CD) control. The etching of low-K dielectric materials was at first approached as if a silicon-based dielectric were being etched. This has not proven particularly effective, as with organic low-K films the chemistries and processes needed to effectively etch the material are substantially different than those for traditional silicon or silicon oxide etching. This has proven even more problematic for the etching of organosilicate glass low-K films.
Organosilicate glass low-K films are often etched using etchant gas flows of similar chemical composition to other materials used in the semiconductor manufacturing process. This can render the manufacture of such devices difficult. As integrated circuits geometries continue to shrink, plasma etch processes are required to define these high resolution patterns. The most widely used dry etch technique is Reactive Ion Etching, or RIE, which offers directionality and selectivity together with high throughput.
The etching of high aspect ratio trenches, sometimes referred to as HART, into OSG and other low-K materials is becoming increasingly important for micro- and nano-engineering. One example is in the case of comb-driven structures, trench capacitors, and trench isolation for vertical transistors. The aspect ratio, AR, is defined as the depth of the trench divided by its width. Currently, one of the most commonly implemented techniques for etching HART's is dry reactive ion etching, or RIE.
When etching HART's with RIE it is observed that the etch rate is dependant on time and the mask opening. In general, smaller trench openings are etched more slowly than those which are wider. Accordingly, large features etch at a faster rate than small features. This effect is known as RIE lag and apparently depends on the AR of the trench rather than on the depth or width of the trench.
Prior efforts at etching vias and other structures in wafers incorporating OSG have generally utilized some form of Ar/C
4
F
8
/O
2
etch chemistry. In general, these attempts have met with poor results. Many of these different processes resulted in either severe reverse RIE lag, poor via profiles, nonuniformity at high etch rates, or poor resist selectivity.
What is needed is a process chemistry for etching features in wafers incorporating OSG dielectrics which process results at once in minimal RIE lag, minimal bowing of the features formed by the etch process, good etch profiles, good resist selectivity, and good etch uniformity across the wafer.
It would be desirable if the methodology were capable of implementation on existing semiconductor etch equipment.
SUMMARY OF THE INVENTION
The present invention teaches a process chemistry for etching features in wafers incorporating OSG dielectrics which process results at once in minimal RIE lag, minimal bowing of the features formed by the etch process, good etch profiles, good resist selectivity, and good etch uniformity across the wafer. In order to provide these desirable results, a novel etch gas mixture, including CH2F2 and CF4 is employed. According to one embodiment of the present invention, this novel gas mixture is employed as part of a three-step etch process wherein the several etch steps have varying degrees of etch selectivity between wafer components.
The methodology of the present invention is capable of implementation on a wide variety of existing semiconductor etch equipment.
These and other advantages of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the Drawing.


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