Process for etching tapered vias in silicon dioxide

Details Process for etching tapered vias in silicon dioxide Process for etching tapered vias in silicon dioxide

1982-11-18

1984-07-24

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156643, 156646, 156651, 156653, 156657, 1566591, 156662, 204192E, 427 90, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

044616724

ABSTRACT:
A method for etching tapered apertures in the insulating layer between metal layers in an integrated circuit having a multilevel interconnection system. In one embodiment a thin layer of polysilicon is formed on the interlevel oxide layer followed by deposition of a photoresist layer thereon. A pattern of apertures is formed in the resist layer which is then exposed to a selective silicon etchant to form an opening in the polysilicon layer extending to the surface of the oxide layer. The polysilicon and oxide layers are then etched with a nonselective etchant. During the oxide etch the polysilicon is etched laterally, thereby widening the apertures and producing a taper in the aperture sidewalls as the etch proceeds. The magnitude of the taper is related to the thickness of the polysilicon layer. In another embodiment wherein the oxide layer directly overlies a silicon region, the polysilicon and oxide layers are first exposed to a nonselective etchant to etch partially through the oxide layer. The tapered via is completed by etching through the oxide layer with a selective etchant.

REFERENCES:
patent: 3880684 (1975-04-01), Abe
patent: 4076575 (1978-02-01), Chang
patent: 4184909 (1980-01-01), Chang
patent: 4213818 (1980-07-01), Lemons et al.
patent: 4293375 (1981-10-01), Neukomm

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