Process for etching a silicon nitride hardmask mask with zero et

Details Process for etching a silicon nitride hardmask mask with zero et Process for etching a silicon nitride hardmask mask with zero et

1998-02-19

2000-08-15

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438696, 438780, 438950, 438725, H01L 21762

Patent

active

061035963

ABSTRACT:
A method for controlling the mask bias of a photoresist mask is described whereby a polymer coating is formed over the patterned photoresist mask immediately prior to etching the mask's pattern into a subjacent layer. The polymer coating is formed by treatment of the photoresist mask with a plasma, struck in within a reactive ion etching tool, in a gas mixture containing chlorine and helium. The etch durability and the thickness of the polymer coating determines the dimensional bias of the mask with respect to the pattern formed in the subjacent layer. By varying the polymer formation parameters a controllable etch bias between -0.01 and +0.03 microns can be achieved. This capability is particularly useful for patterning in integrated circuits where critical dimensions approach the resolution limits of the photolithography. The method is applied to the patterning of a silicon nitride hardmask employed in the formation of field oxide isolation (LOCOS) where a zero bias condition is achieved. The polymer coating can be formed in the same tool that is used to etch the hardmask, making the process simple and cost effective.

REFERENCES:
patent: 4613400 (1986-09-01), Tam et al.
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4803181 (1989-02-01), Buchmann et al.
patent: 4855017 (1989-08-01), Douglas
patent: 5342481 (1994-08-01), Kadomura

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