Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-06-23
2001-08-07
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C719S323000, C719S323000, C252S079100
Reexamination Certificate
active
06271144
ABSTRACT:
The present invention relates in a general way to the field of high-density plasma etching for the production of submicron structures used in microelectronics.
More particularly, a process for anisotropically etching an Si
1−x
Ge
x
(0<×≦1) layer and, in particular, a stack of layers comprising an Si
1−x
Ge
x
first layer and, on this first layer, a silicon second layer, by high-density plasma is herein described.
The material generally used for forming the gate of a CMOS semiconductor device, in particular in the case of devices with a short channel, ≦0.18 &mgr;m, is amorphous silicon (a-Si). Conventionally, the gates of these devices are obtained by high-density plasma etching an a-Si layer deposited on a thin silicon oxide layer (gate oxide) formed on the surface of a silicon substrate. This etching step must be anisotropic in order for the side walls of the a-Si feature finally obtained to be perfectly straight so as to meet the size imposed by the mask defined beforehand by a photolithography step. Moreover, and this is one of the main difficulties with the step of etching the gate of a CMOS device, the subjacent silicon oxide must not be punctured so as not to damage the future active regions of the device, which means that the consumption of silicon oxide must be as low as possible.
The actual etching step includes exposing the layer of material to be etched, for example a-Si, on which a masking pattern has been formed beforehand by photolithography, to a reactive plasma using a gas or a gas mixture which reacts chemically with the material to be etched in order to form volatile reaction products which desorb spontaneously or under the influence of the ion bombardment. The etching kinetics observed in plasmas depend, on the one hand, on a phenomenon of dissociation of the gas or gas mixture which generates the reactive atomic species and, on the other hand, on the ionization of the gas or gas mixture which produces positive ions allowing ion bombardment normal to the surface of the substrate which is at a negative potential with respect to the potential of the plasma.
The actual etching operation is induced by the plasma, the etching action of which may be decomposed into a vertical etch rate Vv of direction normal to the surface of the substrate and a spontaneous lateral etch rate Vl, directed towards the etching side walls not exposed to the ion bombardment.
In practice, in order to obtain an anisotropic etching profile, it is known that the ion bombardment must be intense and of high energy so as to favour the vertical etch rate Vv enhanced by the ion bombardment and to minimize the spontaneous lateral etch rate Vl, i.e. the spontaneous etching reactions between etching side walls and reactive species in the plasma. Etching anisotropy is obtained in some cases by forming a thin passivation layer on the side walls of the etched feature, thereby protecting the side walls of the etched feature from being spontaneously etched by the reactive species produced by the discharge.
In the specific case of etching a-Si, it is necessary to obtain, on the one hand, aniosotropic etching and, on the other hand, to minimize the consumption of gate oxide. The processes for etching a-Si generally includes three steps.
The first step, during which the bias energy applied to the substrate is high (typically, in an industrial high-density plasma source whose ion density is between 5×10
11
and 10
12
ions/cm
3
, the bias power applied to a 200 mm diameter substrate is 400 W), makes it possible to etch the thin native silicon oxide layer which forms naturally on the surface of a-Si exposed to air.
The second step, which is called the main etching step, makes it possible to obtain the anisotropy of the etching profile: the bias power for a 200 mm diameter substrate is then between 100 and 150 W, depending on the high-density plasma sources used.
The third step is only initiated when an end-of-etch detection signal is obtained at the completion of the main etching step and therefore only when the entire a-Si is etched in the open regions of the substrate (i.e., the featureless regions). This step, which is called the overetching step, is necessary in order to complete the etching in the dense regions of the substrate, i.e. those regions in which the gates may be separated by a distance of less than 0.5 micrometres. This is because, in these dense regions, the a-Si etch rate may be up to 20-30% lower than in the open regions. The overetching step must therefore be long enough to allow the a-Si remaining after the main etching step to be etched, whatever the point on the substrate. In practice, its duration represents 50% of the time for the main etching step and may be extended up to 100% in the case of topographically severe substrates. During this step, the gate oxide is exposed to the plasma in the open regions. The plasma conditions must therefore be adjusted so as not to damage it. In practice, the bias power applied to the 200 mm diameter substrate is reduced to values below 60 W so as to decrease the ion energy substantially and there-ore to increase the selectivity between the a-Si and the silicon oxide (the selectivity is defined as the ratio of the etch rates).
The chemistry used for etching the amorphous silicon generally uses gases such as Cl
2
, HBr, HCl, Br
2
. In order to preserve the gate oxide, O
2
is added to the gas phase (during the overetching step or possibly during the entire process) in order to increase the a-Si/gate oxide selectivity. The most commonly employed chemistries for etching a-Si are the mixtures HBr/Cl
2
/O
2
and HBr/O
2
. Each gas in the mixture has a very precise role: chlorine is used to obtain a high etch rate and is conducive to the creation of anisotropic etching profiles (atomic chlorine, produced by the discharge, does not react spontaneously with the a-Si of the etching side wall). One of the drawbacks of using chlorine is that it increases the etch rate of a-Si at the edge of the gates (a phenomenon more widely known in plasma etching as “trenching”). As a result, the silicon oxide at the edge of the gate may be exposed to the plasma before the end-of-etch detection signal for the main etching step. In the case of very thin (thickness <5 nm) gate silicon oxide layers, this increase in the etch rate at the edge of the gates may puncture the oxide at the edge of the gates. The addition of HBr to the gas phase allows this phenomenon to be reduced. This is because adding HBr (which produces this phenomenon to a lesser extent than chlorine) allows the partial pressure of chlorine in the gas phase to be decreased and therefore the magnitude of the phenomenon to be decreased. HBr also allows the a-Si/gate oxide selectivity to be substantially increased. Oxygen, which markedly improves the a-Si/gate oxide selectivity, is also conducive to the formation of a passivation layer which protects the a-Si side walls during etching. This passivation layer is a highly chlorinated substoichiometric oxide whose composition is approximately SiOCl. The exact composition and the thickness of this oxide may depend on the high-density plasma source used and on the gas mixture, but the etching of a-Si is always anisotropic when this passivation layer is formed on the etching side walls.
It has been proposed to replace amorphous silicon as the material for the gate of a CMOS semiconductor device, in particular for the fabrication of devices with a short (≦0.18 &mgr;m) channel, with a stack of a polycrystalline silicon-germanium (Si
1−x
Ge
x
, 0<×≦1) first layer deposited directly on the gate oxide. A silicon, for example polycrystalline silicon, second layer is generally deposited on this polycrystalline silicon-germanium first layer. The essential advantage of replacing the a-Si layer with this polycrystalline silicon-germanium/silicon (poly Si
1−x
Ge
x
/Si) stack is that a gate is obtained which, using a single p
+
doping, replaces the twin, n
+
and p
+
, gates used for obtaining PMOS and
Joubert Olivier
Monget Cédric
Vallon Sophie
Conley Rose & Tayon PC
France Telecom
Umez-Eronini Lynette T.
Utech Benjamin L.
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