Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1996-04-04
1998-03-17
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438649, 438655, H01L 21283, H01L 21336
Patent
active
057286256
ABSTRACT:
The present invention is directed to a process for device fabrication in which a layer of cobalt silicide is formed as a low resistance contact layer over the source and drain regions of a device. The silicon substrate is first subjected to conditions that fore a thin layer of oxide on the surface thereof. It is advantageous if the oxide thickness is about 0.5 nm to about 1.5 nm. At least one layer of cobalt is then formed on at least the oxidized surfaces of the silicon substrate. The cobalt layer(s) is formed using conventional expedients such as e-beam evaporation. The cobalt layer(s) is formed on the substrate in an essentially oxygen free environment. Each cobalt layer has a thickness of about 1 nm to about 5 nm. While maintaining the substrate in the essentially oxygen-free environment, the substrate is annealed to form a layer of cobalt silicide. It is advantageous if the substrate is annealed at a temperature in the range of about 450.degree. C. to about 800.degree. C. The cobalt silicide that results has a low resistance and high uniformity that makes it advantageous for use as a contact material.
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"New Silicidation Technology by SITOX (Silicidation Through Oxide", by Sumi, H. et al., IEEE, IEDM Tech Dig., Dec. 1990, pp. 249-252.
"A Manufacturable Process for the Formation of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology", Berti, A.C.,1992 Proc. 9th International VLSI Multilevel Interconnection Conference(VMIC), pp. 267-273, (Jun. 9-10, 1992).
Botos Richard J.
Lucent Technologies - Inc.
Quach T. N.
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