Process for design of semiconductor circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C716S030000, C430S005000, C430S030000

Reexamination Certificate

active

07861195

ABSTRACT:
The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

REFERENCES:
patent: 7448018 (2008-11-01), Heng et al.
patent: 2004/0210863 (2004-10-01), Culp et al.
patent: 2004/0261044 (2004-12-01), Yonezawa
patent: 2005/0251771 (2005-11-01), Robles
patent: 2008/0071511 (2008-03-01), Lin

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