Process for defining the width of silicon gates using spacers as

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

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438947, H01L 213205

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active

061036056

ABSTRACT:
Process for controllably defining the width of silicon gates to critical dimensions. The process includes steps of first providing a semiconductor substrate (e.g. a silicon wafer) with a gate oxide layer on its surface, followed by depositing a silicon (e.g. polysilicon or amorphous silicon) gate layer on the gate oxide layer. A first oxide layer (e.g. a PSG, TEOS-based or silane-based oxide layer) is then formed on the silicon gate layer. Next, the first oxide layer is patterned to form a patterned first oxide layer, exposing portions of the silicon gate layer. A second oxide layer is then formed on the patterned first oxide layer and the exposed portions of the silicon gate layer. A first silicon (e.g. polysilicon or amorphous silicon) layer is subsequently formed on the second oxide layer. The first silicon layer is then patterned to form a patterned first silicon layer with sidewalls, exposing portions of the second oxide layer. A conformal spacer precursor layer (e.g. of Si.sub.3 N.sub.4 or PSG) is subsequently formed over the patterned first silicon layer and the exposed portions of the second oxide layer. The conformal spacer precursor layer is then etched to form spacers on the sidewalls. The patterned first silicon layer is then removed, followed by the removal of exposed portions of the second oxide layer. The silicon gate layer is subsequently etched, using at least one of the spacers as an etch hard mask, to define silicon gates of critical dimensions less than 0.10 micron.

REFERENCES:
patent: 4313782 (1982-02-01), Sokoloski
patent: 4489481 (1984-12-01), Jones
patent: 5496750 (1996-03-01), Moslehi
patent: 5514609 (1996-05-01), Chen et al.
patent: 5770506 (1998-06-01), Koh
patent: 5950091 (1999-09-01), Fulford, Jr. et al.
Wolf, S., et al.: Silicon Processing For The VLSI Era, vol. 1,Process Technology, pp. 185, 522, Lattice Press, (1986).

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