Process for controlling a memory-plane refresh of a dynamic rand

Details Process for controlling a memory-plane refresh of a dynamic rand Process for controlling a memory-plane refresh of a dynamic rand

1999-02-17

2000-03-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

365203, 365205, 365210, G11C 700

Patent

active

060381876

ABSTRACT:
A process is for controlling a memory-plane refresh of a dynamic random-access memory. After having selected at least one first reference memory cell structurally similar to the memory cells of the memory plane, to store a first predetermined binary information item therein, the voltage across the terminals of the storage capacitor of this first reference memory cell is compared with a first predetermined reference voltage. When the voltage reaches the reference voltage, a control signal is delivered in response to which the memory plane is refreshed, then the first reference memory cell is again selected in order to refresh its contents.

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patent: 5912856 (1999-06-01), Lee et al.
patent: 5936904 (1999-08-01), El Hajji

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