Plastic article or earthenware shaping or treating: apparatus – Distinct means to feed – support or manipulate preform stock... – Female mold type means
Reexamination Certificate
1999-06-21
2001-03-13
Chaudhuri, Olik (Department: 2811)
Plastic article or earthenware shaping or treating: apparatus
Distinct means to feed, support or manipulate preform stock...
Female mold type means
C264S272170, C257S724000, C257S787000, C425S544000
Reexamination Certificate
active
06200121
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a packaging technology and, more particularly, to a process for molding semiconductor chips and a molding die used therein.
DESCRIPTION OF THF RELATED ART
Various kinds of package are used for semiconductor devices. A tape ball grid array package, a plastic ball grid array package, a fine pitch ball grid array package and a chip size package are examples of the known package. A surface-mounting package such as the plastic ball grid array package and the chip size package has a ball grid array directly connected to a circuit board, and is appropriate for miniature electric products.
A typical example of the packaging process is disclosed in Japanese Patent Publication of Unexamined Application No. 9-252065. The prior art packaging process starts with preparation of a printed circuit panel. A conductive pattern was printed on an insulating plate of glass fiber reinforced epoxy resin or polyimide, and the conductive pattern and the insulating plate as a whole constitute the printed circuit panel.
The printed circuit panel is placed on a die. A punch is pressed against the printed circuit panel, and cuts a circuit frame from the printed circuit panel. The punch is spaced from the circuit frame, and a scrap is left on the die. The circuit frame is upwardly pushed back, and returns into the hollow space formed in the scrap. The circuit frame is snugly received in the scrap, and does not drop out from the scrap. However, a suitable temporary fastening means may be formed in the scrap.
Subsequently, the semiconductor chip is bonded to the circuit frame pushed back into the scrap, and the conductive wires electrically connect the bonding pads on the semiconductor chip to the conductive pattern of the circuit frame. After the wire bonding, the semiconductor chip bonded to the circuit frame is placed in a cavity formed in a molding die, and melted synthetic resin is introduced into the cavity. The synthetic resin is solidified, and the semiconductor chip is sealed in the plastic package.
The solder balls are formed on the reverse surface of the circuit frame, and the prior art semiconductor device is completed. Upon completion, the semiconductor device is separated from the scrap. Thus, the semiconductor chip is mounted on the circuit frame temporarily fastened to the scrap, and the semiconductor device is separated from the scrap after the molding. Another prior art process is disclosed in Japanese Patent Publication of Unexamined Application No. 9-36155. According to the prior art packaging technology disclosed in the Japanese Patent Publication of Unexamined Application, plural semiconductor chips are mounted on a printed circuit panel at intervals, and frames are fixed to the printed circuit panel in such a manner as to surround the semiconductor chips respectively. The printed circuit panel is cut into substrates where the semiconductor chips are respectively mounted. The semiconductor chip mounted on the substrate is located inside the frame, and the peripheral area of the substrate is outside the frame. The substrate is clamped between an upper die and a lower die, and the frame, the upper die and the lower die define a cavity in the molding die. A gate is formed at a corner of the cavity or a mid point of an edge defining a part of the cavity. Melted synthetic resin is introduced through the gate and the frame into the cavity, and is solidified. As a result, the semiconductor chip is sealed in the molding material.
Yet another prior art process is disclosed in Japanese Patent Publication of Unexamined Application No. 6-244313. The prior art process disclosed in the Japanese Patent Publication of Unexamined Application is used for an SOJ (Small Outline J-bend) package. According to the prior art technology, scratch lines are formed in a semiconductor wafer, and define semiconductor chips. The semiconductor wafer is bonded to a polyimide tape, and bonding pads on the semiconductor chips are connected through conductive wires to leads on the polyimide tape. The semiconductor chips assembled with the leads are put in a cavity formed in a molding die, and melted synthetic resin is introduced into the cavity. The semiconductor chips are concurrently sealed in a large piece of synthetic resin. Grooves are formed in the large piece of synthetic resin, and are located over the scribe lines. The large piece of synthetic resin is broken into products of a semiconductor device along the grooves.
Each of the prior art processes disclosed in Japanese Patent Publication of Unexamined Application Nos. 9-252065 and 9-36155 have the cutting steps, respectively. The circuit frame is cut from the printed circuit panel by using the punch and the die. When the printed circuit panel is clamped by the die, wide area is consumed, and the clamped area makes the circuit frames widely spaced. For this reason, the manufacturer can not arrange the semiconductor chips on the printed circuit panel at high dense. The other prior art process requires an area occupied by the frames and another area consumed by the punch. Therefore, the manufacturer roughly arranges the semiconductor chips on the panel. The glass fiber reinforced epoxy resin and the polyimide tape are expensive. In fact, the areas occupied by the semiconductor chips are only fifty percent of the total area of the expensive panel. The uneconomical usage of the expensive panel makes the production cost of the semiconductor device high.
On the other hand, a problem is encountered in the prior art process disclosed in Japanese Patent Publication of Unexamined Application No. 6-244313 in the scratch lines on the semiconductor wafer and voids after the molding. It is necessary for the manufacturer to form the scratch lines accurately under the grooves. This means an accurate positioning. If the scratch lines are deviated from the grooves, the semiconductor chips are liable to be damaged in the separation stage. Moreover, the grooves are formed during the molding, and projections are formed in the molding dies. The projections are an obstacle against the melted synthetic resin flowing into the cavity, and the voids are produced in the large piece of synthetic resin due to the non-smooth flow of the melted synthetic resin. The prior art process is used for the SOJ package. It is difficult to use the prior art process for a large-sized package and in a concurrent molding for a large number of semiconductor chips.
Finally, all the prior art processes are used in the packaging for semiconductor chips of a certain size. If the semiconductor chips to be molded are different in size from those usually molded, the manufacturer requires a new molding die. Moreover, the plastic ball grid array package and the chip size package have not been standardized, yet. On the other hand, various integrated circuit devices are to be sealed in those packages. The manufacturer requires different molding dies for those semiconductor integrated circuit devices. The molding dies are expensive, and increase the production cost.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a process, which is economical and improves the yield.
It is also an important object of the present invention to provide a molding die, which is used in the process.
Research and development efforts have been made on an economical process by the assignee of the present invention. The economical process had the steps of arranging semiconductor chips on a circuit panel, sealing the semiconductor chips on the circuit panel in a large piece of molding material and cutting the molded product into products of a semiconductor device. However, the assignee noticed that known molding dies were causative of voids and wire weep. The known molding die had a gate opposite to a semiconductor device. When plural gates were formed in a molding die in such a manner as to be opposite to semiconductor chips, respectively, melted synthetic resin tended to flow into the gaps between the semiconductor chips, and did not fill the space
Chambliss Alonzo
Chaudhuri Olik
Hutchins, Wheeler & Dittmar
NEC Corporation
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