Process for borderless stop in tin via formation

Details Process for borderless stop in tin via formation Process for borderless stop in tin via formation

1999-11-22

2002-01-15

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S700000, C438S703000

Reexamination Certificate

active

06339027

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to forming via plugs in semiconductor devices, and more specifically to forming via plugs to borderless structure semiconductor devices.
BACKGROUND OF THE INVENTION
As the design rule for semiconductor devices constantly decreases, borderless structures, such as contacts, have been begun to be used to permit the further microminiaturization. However, the use of borderless structures requires a level and degree of accuracy in fabricating these devices that is not met to achieve acceptable yields. Misaligned via openings can create metal via plugs formed in contact with sidewalls of metal lines that degrade the electromigration of the metal via plugs.
U.S. Pat. No. 5,920,792 to Lin describes an etch stop over an HDP-CVD oxide layer. A first HDP-CVD oxide layer is formed over a metal wiring structure having a gap. A second HDP-CVD oxide layer is formed over the first HDP-CVD oxide layer. The second HDP-CVD oxide layer having lower etching/depositing component ratio, and thus a higher CMP removal rate, than the first HDP-CVD oxide layer. A thin CMP passive layer may be deposited over the second HDP-CVD oxide layer. The thin CMP passive layer having the same etching/depositing component ratio as the second HDP-CVD oxide layer. The structure is chemical-mechanically polished (CMP) wherein: the thin CMP passive layer minimizes dishing in the recessed areas and is removed; the second HDP-CVD oxide layer is polished and removed by CMP until the first HDP-CVD oxide stop layer is reached resulting in an essentially planar surface.
U.S. Pat. 5,904,569 to Kitch describes a process of forming self-aligned vias in multi-metal integrated circuits using self-aligned metal pillars to connect metal layers separated by a dielectric. The metal pillars comprise a first aluminum (Al) layer, a middle titanium nitride (TiN) layer that acts as an etch stop layer, and an upper Al layer.
U.S. Pat. No. 5,891,799 to Tsui describes a method for making stacked and borderless via structures on multilevel metal interconnections for integrated circuits.
U.S. Pat. No. 5,840,624 to Jang et al. describes a method for forming a borderless contact or via hole in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric (ILD) layer during the opening of the borderless contact or via hole in an overlying ILD layer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures.
Another object of the present invention is to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures using etch stop layers over the borderless structures.
A further object of the present invention is to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures without the need to mask and etch the SiN etch stop layer.
Yet another object of the present invention is to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures using a self-aligned SiN etch barrier that prevents inter-metal shorts otherwise due to via over-etch.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an upper first oxide layer and at least two metal lines formed on the upper oxide layer are provided. The metal lines are spaced apart a predetermined distance and each having a lower barrier layer, a middle layer, and an upper etch stop layer. A second oxide layer is deposited over the first oxide layer and the pair of metal lines. An etch barrier layer is formed over the second oxide layer. The structure is planarized to form openings in the etch barrier layer over the metal lines. A third oxide layer is deposited and patterned over the planarized structure to form via openings through the etch barrier layer openings to the upper etch stop layers on the metal lines. Metal via plugs are formed in the via openings.


REFERENCES:
patent: 5485035 (1996-01-01), Lin et al.
patent: 5494854 (1996-02-01), Jain
patent: 5545581 (1996-08-01), Armacost et al.
patent: 5757077 (1998-05-01), Chung et al.
patent: 5840624 (1998-11-01), Jang et al.
patent: 5891799 (1999-04-01), Tsui
patent: 5904569 (1999-05-01), Kitch
patent: 5920792 (1999-07-01), Lin
patent: 0564136 (1993-10-01), None

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