Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-08-07
2007-08-07
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S109000, C438S928000, C438S459000, C257S777000, C257S723000, C257S686000, C257SE21705
Reexamination Certificate
active
10256336
ABSTRACT:
A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.
REFERENCES:
patent: 4800459 (1989-01-01), Takagi et al.
patent: 4912844 (1990-04-01), Parker
patent: 5032896 (1991-07-01), Little et al.
patent: 5065277 (1991-11-01), Davidson
patent: 5128831 (1992-07-01), Fox et al.
patent: 5161093 (1992-11-01), Gorczyca et al.
patent: 5284548 (1994-02-01), Carey et al.
patent: 5312765 (1994-05-01), Kanber
patent: 5324687 (1994-06-01), Wojnarowski
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5426563 (1995-06-01), Moresco et al.
patent: 5485038 (1996-01-01), Licari et al.
patent: 5489554 (1996-02-01), Gates
patent: 5545291 (1996-08-01), Smith et al.
patent: 5609907 (1997-03-01), Natan
patent: 5701233 (1997-12-01), Carson et al.
patent: 5751018 (1998-05-01), Alivisatos et al.
patent: 5772905 (1998-06-01), Chou
patent: 5783856 (1998-07-01), Smith et al.
patent: 5800650 (1998-09-01), Anderson et al.
patent: 5824186 (1998-10-01), Smith et al.
patent: 5861670 (1999-01-01), Akasaki
patent: 5877550 (1999-03-01), Suzuki
patent: 5904545 (1999-05-01), Smith et al.
patent: 5952588 (1999-09-01), Young
patent: 5998875 (1999-12-01), Bodo et al.
patent: 6037255 (2000-03-01), Hussein et al.
patent: 6081988 (2000-07-01), Pluymers et al.
patent: 6096386 (2000-08-01), Biebuyck et al.
patent: 6130823 (2000-10-01), Lauder et al.
patent: 6165911 (2000-12-01), Calveley
patent: 6166438 (2000-12-01), Davidson
patent: 6188127 (2001-02-01), Senba et al.
patent: 6239482 (2001-05-01), Fillion et al.
patent: 6294741 (2001-09-01), Cole, Jr. et al.
patent: 6306680 (2001-10-01), Fillion et al.
patent: 6326058 (2001-12-01), Biebuyck et al.
patent: 6500694 (2002-12-01), Enquist
patent: 6541346 (2003-04-01), Malik
patent: 6579463 (2003-06-01), Winningham et al.
patent: 6586338 (2003-07-01), Smith et al.
patent: 6611237 (2003-08-01), Smith et al.
patent: 6656568 (2003-12-01), Winningham et al.
patent: 6946322 (2005-09-01), Brewer
patent: 6984571 (2006-01-01), Enquist
patent: 2002/0005294 (2002-01-01), Mayer et al.
patent: 2002/0045030 (2002-04-01), Ozin et al.
patent: 2003/0062123 (2003-04-01), Hunter et al.
patent: 2003/0068519 (2003-04-01), Brewer et al.
patent: 2003/0112576 (2003-06-01), Brewer et al.
patent: 0 982 385 (2000-03-01), None
patent: 10-022338 (1998-01-01), None
patent: 01/33300 (2001-05-01), None
Chou, Stephen Y., et al, “Imprint of Sub-25 NM Vias and Trenches in Polymers,”Applied Physics Lett., American Institute of Physics, vol. 67, No. 21, pp. 3114-3116 (Nov. 20, 1995).
Chou, Stephen Y., et al, “Nanoimprint Lithography,”J. Vac. Sci. Technol. B, American Vacuum Society, vol. 14, No. 6, pp. 4129-4133 (Nov./Dec. 1996).
“Method to Control the Geometry and Vertical Profile of Via Holes in Substrate Materials,”IBM Technical Disclosure Bulletin, vol. 35, No. 5, pp. 211-216 (Oct. 1992).
Terfort, Andreas, et al, “Self-Assembly Of An Operating Electrical Circuit Based On Shape Complementary And The Hydrophobic Effect,”Advanced Materials, vol. 10, No. 6, pp. 470-473, (1998).
Terfort, Andreas, et al, “Three-Dimensional Self-Assembly of Millimetre-Scale Components,”Nature, vol. 386, pp. 162-164, (Mar. 13, 1997).
“Use of High Precision Silicon Molds for Replicating Microelectronic Packaging Structures,”IBM Technical Disclosure Bulletin, vol. 30, No. 5, pp. 306-311 (Oct. 1987).
Borzenko, T., et al., “Polymer bonding process for nanolithography,”Applied Physics Letters, vol. 79, No. 14, pp. 2246-2248 (Oct. 1, 2001).
Chou, S.Y., et al., “Imprint of sub-25 nm vias and trenches in polymers,”Appl. Phys. Lett., 67, No. 21, pp. 3114-3116 (Nov. 20, 1995).
Chou, S.Y., et al., “Nanoimprint lithography,”J. Vac. Sci. Technol. B, vol. 14, No. 6, pp. 4129-4133 (Nov./Dec. 1996).
Tormen, M., et al., “Thermocurable polymers as resists for imprint lithography,”Electronics Letters, vol. 36, No. 11, pp. 983-984 (May 25, 2000).
Zhang, W., et al., “Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers,”Applied Physics Letters, vol. 79, No. 6, pp. 845-847.
Bobbio, S.M., et al., “Integrated Force Arrays,”IEEE Proceedings of the Workshop on Micro Electro Mechanical Systems(MEMS), Fort Lauderdale, pp. 149-154 (Feb. 7-10, 1993).
Srinivasan, U., et al., “Fluidic Self-Assembly of Micromirrors onto Surface Micromachined Actuators,”IEEE, pp. 59-60, (2000).
Srinivasan, U., et al., “Microstructure to Substrate Self-Assembly Using Capillary Forces,”Journal of Microelectromechanical Systems, vol. 10, No. 1, pp. 17-24 (Mar. 2001).
Hao, E., et al., “Buildup of Polymer/Au Nanoparticle Multilayer Thin Films Based on Hydrogen Bonding,”Chem. Mater., vol. 12, No. 11, pp. 3392-3396 (2000).
Kumar, A., et al., “Pattering Self-Assembled Monolayers: Applications in Materials Science,”Langmuir, vol. 10, No. 5, pp. 1498-1511 (1994).
U.S. Appl. No. 10/888,169, filed Jul. 8, 2004, Brewer.
Böhringer, K.F., et al., “Modeling of Capillary Forces and Binding Sites For Fluidic Self-Assembly,”MEMS: 2001: The 14th IEEE International Conference on Micro Electro Mechanical Systems, pp. 369-374 (2001).
Cohn, M.B., et al., “Microassembly Tehnologies For MEMS,”SPIE Micromachining and Microfabrication, Conference on Micromachining and Microfabrication Process Technology IV, Santa Clara, CA, 15 pages total (Sep. 21-22, 1998).
Gracias, D.H., “Forming Electrical Networks In Three Dimensions by Self-Assembly,”Science, vol. 289, pp. 1170-1172 (Aug. 18, 2000).
Hadley, M.A., “Vertical-Cavity Surface-Emitting Laser Diodes: Design, Growth, Mode Control and Integration by Fluidic Self-Assembly,”UMI Dissertation Services, Sections 5.4, 5.5, and 5.6, pp. 75-81 (1994).
Saitou, K., et al., “Externally Resonated Linear Microvibromotor For Microassembly,”Journal of Microelectromechanical Systems, vol. 9, No. 3, pp. 336-346 (Sep. 2000).
Brewer Peter D.
Case Michael G.
Hunter Andrew T.
Matloubian Mehran
Pobanz Carl W.
Anya Igwe U.
Baumeister B. William
HRL Laboratories LLC
Ladas & Parry
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